SU1192071A1 - Device for controlling self-excited inverter consisting of rectifier bridges - Google Patents

Description

The invention relates to power converter technology and is intended for digital control of autonomous inverters (current, voltage), the output voltage of which is regulated by the vector summation method. . . .

The purpose of the invention is to simplify the device.

FIG. 1 shows a structural 10 'diagram of the device; in fig. 2 - timing diagrams illustrating the operation of the device.

Clock 1 is connected to scan counter 2. 15

The low-order outputs of the scan counter 2 and the control code sensor 3 are connected to the digital comparison element 4, and the high-level outputs of the scan counter and the control code sensor 20 are connected to the additional digital comparison element 5.

. The scan counter is connected to a counting trigger .6, the output of which and the high-order outputs of the scan-25 counter are connected to the additional decoder 7 and the second conjunctor 8, the input of which is also connected to the output of the digital comparison element 4 also connected to six The output of which is connected to the decoder 10. The installation inputs of the lower digits of the counter 9. at six through the first conjunctor 11 are connected to the outputs of both digital elements 35 comparison 4 and 5, and the installation input of the senior digit with the output of the second conjunction ora 8.

Timing Charts Illustrated 40

devices for the operation are shown in Fig. 2. * 12 is the code of the scan counter 2 '13 - the control code for the source. nickname 3; 14 - the value of the low bits of the control code; <15 - position / 45 additional decoder 7; 16 of the position of the decoder 10. The discretization of the codes in figure 2 is not shown, the codes are represented by their "weight" equivalent. 50

The principle of operation of the device is as follows. When the pulses of the generator 1 are received, the sweep counter is filled (diagram 12), 55

full counter filling occurs.

about

at 180 period of the output frequency. Frequency clock generator

should be chosen such that for 1/6 period of the output frequency code changed

about and

the number 2, where η - a positive integer, and the total volume scanning counter 3 2 · ^Π, · volume of 2 ⁿ LSBs. Counting trigger 6, connected to the output of the sweep counter. 2 generates a signal that fixes the numbers of half cycles of the output voltage. Senior bits of the counter 2 and the counting trigger 6 control the operation of the additional decoder 7, which switches after 60 'and cyclically distributes the control pulses to the thyristors of the first inverter, the power part of which is made according to a three-phase bridge circuit (not shown) The numbers of the valves entering the operation are determined by the operation.

'decoder 7 and marked on chart 15.'

. The control pulses of the second inverter must be offset relative to the first by an angle φ, change ¹ o

ranging from 0 to 180. The device uses a vertical control principle, for e, the scan counter code (diagram 12) is compared with the control code from the control code source 3 as a parallel code (the source of the control code can be made in the form of a code converter, analog-digital converter or code can be a control computer). When they are equal in all digits, both digital elements of comparison (moment) work simultaneously. The operation of both digital comparison elements is fixed by the first conjunctor 11. In this case, from the output of the main digital comparison element, an input pulse arrives at counter 9 at six, causing the counter to switch. At the same time, the low bits of the counter (three in volume) are set to the zero position, corresponding to issuing 10 control pulses to the 1st or 4th valve of the second inverter via the decoder (diagram 16). At the moment, the digital element of comparison 4 again fixes the equality of the lower digits of the sweep counter code (diagram 12) and the control code (diagram 14), with the counter 9

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six switches to the new position corresponding to the issuance of control pulses to the valves of the 2nd or

5th second inverter. Thus, the counter 9 is switched every 5 ° through 5, providing a consistent output of pulses to all the thyristors of the second inverter. The high bit of counter 9 generates a signal that provides a logical selection of the second inverter's gates from one to four, two to five, three to six pairs to set the high discharge of the counter to its initial state, the device operation regularity is used: (p <180 °. Due to this

at the position of the additional decoder "3" (diagram 15) in the second inverter only one or two or three gates can work, which corresponds to the zero position of the high digit of the counter 9. Therefore, when the digital comparison element 4 is activated, the position of the high digit of the counter 9 is set at this interval signal from the second conjunctor 8.

Thus, using the vector summation method, one can simplify the device for controlling an inverter consisting of two valve bridges. ,

Claims (1)

A DEVICE FOR CONTROLLING A AUTONOMOUS INVERTER CONTAINING FROM TWO VENTILATION BRIDGES, containing a clock generator connected to a sweep counter, the outputs of the lower digits of which are connected to the first inputs of the digital reference element, the second inputs of which are connected to the outputs of the lower bits control code sensor bits, the output through the counter for six is connected to the decoder, characterized in that, for the purpose of simplification, it is equipped with an additional digital comparison element, a counting trigger, an additional decoder and two conjunctors, and the inputs of the additional digital comparison element are connected to the outputs of the two senior the bits of the control code sensor and the sweep counter, the outputs of both digital comparison elements through the first conjunctor are connected to the installation inputs of the lower bits of the counter on the high side there is, the input of the counting trigger is associated with the output of the high-order discharge of the scan counter, the outputs of the higher-order discharge of the counter · the sweep and the output of the counting trigger are associated with the additional decoder and the second 'conjunctor, whose input is also connected with the output of the digital comparison element, and the output with the installation input of the higher-order counter to six. 1 1192071 2