SU708498A1

SU708498A1 - Staicase voltage generator

Info

Publication number: SU708498A1
Application number: SU772484047A
Authority: SU
Inventors: Владлен Аркадьевич Брагинский; Юрий Борисович Нестеров
Original assignee: Предприятие П/Я Г-4175
Priority date: 1977-05-10
Filing date: 1977-05-10
Publication date: 1980-01-05

Description

Изобретение относитс к радиотехнике, импульсной технике и может быть использовано в устройствах автоматики. Известен генератор ступенчатого напр жени , содержащий основные и коммутирующие ключи, регистры сдвига, задающий генератор Недостатком данного устройства вл етс его низка линейность формируемого напр жени . Наиболее близким техническим решением вл етс генератор ступенчатого напр жени , содержащий делитель частоты, задающий генератор импульсов, выход которого подключен к первому входу первого накапливающего сум матора непосредственно, а к первому входу формировател команд через последовательно соединенные двоичный счетчик и дешифратор, второй вход накапливающего сумматора подкл чен к первому выходу блока установки кодов первый преобразователь код - напр жение, входом подключенный к выходу первого накап ливающего сумматора 2. Недостатком данного устройства вл етс низка точность согласовани управл ющего напр жени с перестроечной характеристикой при.емника. Цель предлагаемого изобретени - повыщение точности согласовани управл ющего напр жени с перестроечной характеристикой приемника. Дл этого в генератор ступенчатого напр жени введены преобразователь код-напр жение , управл емый генератор высокой частоты, смеситель, злемент регистрации и второй накапливающий сумматор, первый вход которого подключен к выходу задающего генератора импульсов , второй вход - ко второму выходу блока установки кодов, третиц вход - к третьему входу первого накапливающего сумматора и к выходу статического регистра, вход которого подключен к третьему выходу блока установки кодов, четвертый вход - к первому выходу .формировател команд, второй вь1ход которого подключен к четвертому входу первого накапливающего сумматора, первый вход - ко второму входу двоичного счетчика, . второй вход - к выходу злемента регистрации и ко входу делител частоты, выход которого подключен к п тому входу первого накапливающего сумматора, к третьему входу двоичного счетчика и к п тому входу второго накапливающего сумматора, выходом подключенного к.первому входу смесители через последовательно соединенные второй преобратователь код-напр жение , и управл емый генератор высокой частоты, второй вход смесител вл етс входом устройсгва, выход подключен ко входу элемента регнстрадии.The invention relates to radio engineering, pulse technology and can be used in automation devices. A step voltage generator is known that contains primary and switching keys, shift registers, a master oscillator. The disadvantage of this device is its low linearity of the voltage being formed. The closest technical solution is a step voltage generator, containing a frequency divider, a master pulse generator, the output of which is connected to the first input of the first sum-accumulator and directly to the first input of the command generator via serially connected binary counter and decoder, the second input of the accumulating adder To the first output of the installation block of codes, the first converter code is a voltage, the input connected to the output of the first accumulator adder 2. Failure The driver of this device is the low accuracy of matching the control voltage with the resetting characteristic of the receiver. The purpose of the present invention is to increase the accuracy of matching the control voltage with the receiver tuning characteristic. For this purpose, a code-voltage converter, a controlled high-frequency generator, a mixer, a recording element and a second accumulating adder, the first input of which is connected to the output of the master pulse generator, the second input - to the second output of the code setting block, are entered into the step voltage generator. input - to the third input of the first accumulating adder and to the output of the static register, the input of which is connected to the third output of the code setting block, the fourth input - to the first output of the command former, W v1hod swarm is connected to the fourth input of the first accumulator, a first input - to the second input of the binary counter. the second input is connected to the output of the registration element and to the input of the frequency divider, the output of which is connected to the fifth input of the first accumulating adder, to the third input of the binary counter and to the fifth input of the second accumulating adder, the output connected to the first input of the mixers through the second converter connected in series the code-voltage, and the controlled high-frequency generator, the second input of the mixer is the device input, the output is connected to the input of the register element.

На чертеже представлена блок-схема предлагаемого генератора.The drawing shows the block diagram of the proposed generator.

Генератор стуне1гчатого напр жени содержит делитель 1 частоты, задающий генератор 2, первый накапливающнй сумматор 3, формирователь 4 команд, двоичный счетчик 5 импуль-сов , дешифратор 6, блок 7 установки кодов, первый преобразователь 8 код-напр жение, статический регистр 9, второй преобразователь 10 код-напр жение, управл емый генератор 11 высокой частоты, смеситель 12, элемент 13 регистрации, второй накашшвающий сумматор 14.The stunner voltage generator contains a frequency divider 1, a master oscillator 2, a first accumulating adder 3, a driver 4 commands, a binary counter 5 pulses, a decoder 6, a code setting unit 7, a first converter 8, code-voltage, a static register 9, the second a code-voltage converter 10, a high-frequency controlled generator 11, a mixer 12, a recording element 13, a second mowing adder 14.

Генератор работает следующим образом.The generator works as follows.

В начале каждого цикла работы генератор приводитс в исходное состо ние. Двоичный счетчик 5 и делитель 1 частоты обнул ютс .At the beginning of each cycle of operation, the generator is reset. Binary counter 5 and frequency divider 1 are zeroed.

В статический регистр 9 и накапливающие сумматоры 3 и 14 через соответствующие информадионные входы из блока 7 установки кодов записываютс числа начальной установки При этом напр жение на выходе преобразовател 8 обеспечивает настройку гетеродина приемного устройсгва на нижнюю частоту, а напр жение на выходе преобразовател 10 вызывает настройку генератора 11 высокой частоты на половину частотного дискрата перестройки выше нижней частоты. Статический триггер формировател 4 устанавливаетс в единицу, что приводит к про влению на четвертом входе первого накапливающего сумматора разрещающего потенциала. При этом в накапливающем сумматоре 3 иод действием тактирующих импульсов, поступающих на его первый вход с выхода генератора 2, в каждом такте производитс суммирование кода, записанного в сумматоре 3, с кодом хран щимс в статическом регистре 9. Счетный триггер формировател 4 команд устанавливаетс в ноль Это приводит к по влению запрещающего потенциала на четвертом входе второго накапливающего сумматора 14, что преп тствует изменению кода, записанного в сумматоре 14, и изменению частоты выходного напр жени генератора 11 высокой Частоты.Static register 9 and accumulating adders 3 and 14 record the initial setup numbers through corresponding information inputs from block 7 of installation of codes. The voltage at the output of converter 8 ensures the tuning of the local oscillator of the receiver to the lower frequency, and the voltage at the output of converter 10 causes the setting of the generator 11 high frequency to half the frequency disk adjustment above the lower frequency. The static trigger of driver 4 is set to one, which leads to the manifestation of a permitting potential at the fourth input of the first accumulating adder. At the same time, in the accumulating adder 3 iod, the action of the clock pulses arriving at its first input from the output of the generator 2, in each clock cycle, the code recorded in the adder 3 is summed with the code stored in the static register 9. The counting trigger of the command driver 4 is set to zero This leads to the occurrence of a forbidden potential at the fourth input of the second accumulating adder 14, which prevents the code recorded in the adder 14 from changing and changing the frequency of the output voltage of the generator 11 to a high Hour. then you.

Claims

A uniform code increment in each clock in accumulative adder 3 leads to a step change in the voltage at the output of the converter 8. This causes a stepwise increase in the frequency of the output signal of the receive oscillator. At the output of the G2 mixer, a signal is formed whose frequency is equal to the difference between the frequencies of the signals from the receiving device and the high-frequency generator 11. When the clock pulses act on the third input of the accumulating adder 3, the frequency of the signal at the output of the mixer 14 will first decrease to zero, and then begin to increase. Since the tuning frequency of the filter of the registration element 13 is equal to half the frequency discrete, the output sypny of the mixer 12 will first exit the passband of this filter and then, again, will appear in it. In this case, the output of the registration element 13 will generate a pulse, which will go to the second input of the driver 4 commands, which will cause the static trigger to be switched to zero, and the counting trigger to one. At the first output of the driver, there are 4 teams on the Vits forbidding potential, and on the second, the resolving potential. The increment of the code in accumulator 3 will stop, which will stop the local oscillator tuning of the receiving device, which will be rebuilt by one frequency sampler. At the same time, the code begins to accumulate in accumulating adder 14 under the effect of clock pulses arriving at its first input from the output of generator 7. At each step, the code recorded in adder 14 is summed with the code recorded in the static register 9. The code in the adder 14 will cause a step change in the voltage at the output of the converter 10, which will lead to a stepwise frequency tuning of the high frequency generator 11 and a change in the frequency of the output signal of the mixer 12, which is first of a bandpass filter in the element register 13, and then would appear in it. This will cause the pulse at the output of registration element 13 and cause the counting trigger of the driver 4 commands to zero. The state of the static trigger does not change. At the same time, the increase of the code in the adder 14 will stop, which will cause the frequency tuning of the high-frequency generator I to stop. Binary counter 5 and decipher 6 determine the duration of the gate and the tuning of the local oscillator of the receiver to one frequency sampling. The impact on the counting input of the binary counter 5 of a certain number of clock pulses of the generator 7 will cause a pulse at the output of the decoder 6, which will go to the first input of the command generator 4 and the zero reset input of the binary counter 5. At the same time, the static trigger of the command driver 4 will be set to one output (|) of the 4 commands for the Vits resolving potential, as well as reset the binary counter 5. Thus, the installation of the driver 4 commands and the binary counter 5 in Ref one state, then the rearrangement of the local oscillator of the receiving device and the high frequency generator 11 by one frequency sampling is repeated. The division factor of the divider 1 frequency, determined by the number of adjustment steps, is equal to twice the number of pulses produced at the output of registration element 1 in one cycle of operation of the device. In this case, at the end of the work cycle, at the output of the 4 frequency divider, a command will be generated by which the device will be reset to its initial state. Claims of the invention A step voltage generator containing a frequency divider that sets the pulse generator, whose output is connected to the first input of the first accumulating adder directly, and the second input of the command accumulator through the serially connected binary pulse counter and splitter, is connected to the second input of the accumulating sum generator to the first output of the code setting block, the first converter to the voltage, the input connected to the output of the first accumulating adder, characterized in that The goal is to increase the accuracy of matching the control voltage with the receiver tuning characteristic, a static register, a second code-voltage converter, a controlled high-frequency generator, a mixer, a recording element, and a second accumulating adder, the first input of which is connected to the output of the master renepatopa pulses are entered into it. , the second input - to the second output of the code setting unit, the third input - to the third input of the first accumulating adder and to the output of the static register, the input of which is connected to tr the output of the code setting block, the fourth input to the first output of the command driver, the second output of which is connected to the fourth input of the first accumulating adder, the first input to the second input of the binary counter, the second input to the output of the registration element and the input of the frequency splitter whose output is connected to the fifth input of the first accumulating adder, to the third input of the binary counter and to the fifth input of the second accumulating adder, the output of which is connected to the first input of the mixer via serial connection nennye second code-voltage converter zheiie and controllable high-frequency generator, the second input of the mixer is an input device, the output is connected to the input of register element. Sources of information taken into account during the examination 1. USSR author's certificate number 491199, cl. H 03 K 4/02.

2. Forward number 2327158/24, 23,02.76, according to which the decision to issue the author's certificate was made.