SU670019A1 - Method of manufacturing large-scale integration circuits using metal-insulator-semiconductors - Google Patents

Abstract

METHOD OF MAKING BIG INTEGRAL SCHEMES ON MDP-TRANSISTORS, including podzatorny oxidation of the silicon substrate, application of a layer of silicon nitride, formation of a protective mask, ion doping of inactive areas, etching of silicon nitride from them, local oxidation of these areas, drawing of a non-active areas, etching of silicon nitride from them, local oxidation of these areas, drawing of a non-active areas, etching of silicon nitride from them, local oxidation of these areas, drawing of a non-active areas, etching of silicon nitride from them, local oxidation of these areas, drawing of a non-active areas, etching of silicon nitride from them, local oxidation of these areas, drawing of a layer, inactive areas, etching of the silicon nitride from them, local oxidation of these areas, the process of drawing out the active areas of silicon nitride, the local oxidation of these areas tey, deposition of polysilicon, frr of polysilicon gates and interconnects, removal of primary oxide from drain and source areas, diffusion of impurity in them and polysilicon regions, Silicon oxide is produced by pyrolysis, opening the pads and subsequent metallization, characterized in that, in order to increase the yield of suitable circuits, before the operation of applying a layer of silicon nitride in the primary oxide layer, contact windows are opened to ensure subsequent contact of polysilicon with silicon. SP

Description

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Fig. 1 The invention relates to microelectronics and concerns a method for manufacturing large integrated circuits on MFDs using c-channel technology with a silicon gate. In the manufacture of integrated circuits on p-channel transistors, silicon of the p-type is used, and the diffusion regions of the p-type are separated from each other by the p-type region of increased concentration relative to the substrate material. The purpose of the invention is to increase the percentage of yield schemes. Figures 1-8 show the stages of manufacturing large integrated circuits of the Example. As the starting material, a silicon substrate 1 KDB-7.5 Ohm cm thick is taken. . Peroxide-ammonia is made (10: 1 washing. Then gate oxide 2 is formed. Silicon substrate 1 is oxidized in dry oxygen for 110 minutes and annealed in argon for 10 minutes at a temperature of 1050 ° С in a quartz tube of a diffusion furnace. In this case. m grows oxide 2 with a thickness of about 1000A. Using photolithography using a positive photoresist such as PH-7, a pattern is formed and oxide 2 is etched at places 3 not protected by photoresist, thus revealing polysilicon contacts to silicon. A 1: 1 mixture of sulfuric acid and hydrogen peroxide is heated in. After this, peroxide-ammonium washing is carried out and silicon nitride 4 is applied with a thickness of about 600 A. Oxidation is carried out at a temperature in dry oxygen for 5 minutes in a medium of steam for 30 minutes, in a dry oxygen environment for 5 min in a quartz tube of a diffusion furnace, an oxide 5 grows on the surface of silicon nitride 4. On its surface a photoresist mask 6 is formed by photolithography. The resist layer 6 covers the active regions and serves as a mask for subsequent ion implantation with boron. Ion implantation is carried out at a boron ion energy of 100 keV at a dose of 2 µC / cm. In this case, region 7 with an increased boron concentration forms on the inactive regions of the silicon surface, which prevents the formation of inversion regions between diffusion buses and increases the threshold voltage of parasitic transistors. Then, oxide 5 is removed from silicon nitride 2 over regions 7. The oxide is etched in a buffer etchant for 2–2.5 minutes. Next, the photoresist in the sulfur-peroxide mixture is removed and silicon nitride 1 is etched over regions 7. Etching occurs in orthophosphoric acid at a temperature of 140 ° C for 90 minutes. Oxide 5 grown on silicon nitride 4 serves as a mask for etching. The peroxide-ammonia washing is again carried out and the oxidation is carried out at a temperature. for 20 minutes in an oxygen environment, 120 minutes in a pair, and 20 minutes in an oxygen environment. At the same time, silicon oxide 8 with a thickness of about 0.85 µm grows over regions 7. Silicon oxidation does not occur at the active regions, because the silicon nitride 4 lying on them interferes. oxidation. The oxide is then etched off silicon nitride 4 in a buffer etchant for 2.5 minutes and etched nitride 1 in phosphoric acid at a temperature for 90 minutes. After removal of nitride 4, gate oxide 2 and silicon are exposed at points of contact 3.. Next, peroxide-ammonia-washing is carried out and polycrystalline silicon 9 is deposited by decomposing monosilane in hydrogen at 780 ° C. Polysilicon thickness 9 times 0.4 microns. Then polysilicon 9 is oxidized at a temperature of 950 ° C in an oxygen environment for 5 minutes, in a pair of 8 minutes, in oxygen for 5 minutes. At the same time, oxide 10 grows in the order of 800-900A on polysilicon 9, a picture is formed by photolithography, etched oxide 10 in a buffer etchant for 3 minutes and etched by polysilicon 9 from places not protected by oxide GO and photoresist in etching composition 160 ml of HNOj, 160 ml of CHjCOGH, 8 ml of HF 5 ml of a solution of Dj in CHjCOOH (I g in 150 ml). The etching time of 90-150 Ci buffer picker remove the oxide from the surface of the silicon-silicon gate 11 from the drain areas 13, is3

point 14 and interconnects 12. Etching time 4 min.

Peroxide-ammonia washing is carried out and phosphorus is diffused. In this case, areas 13 of the drain 13 and the drain 14 of the gate 11 and the interconnect 12 are doped. The diffusion is carried out at a temperature from the vapor phase. Source of diffusion - POClj,

Then, peroxide-ammonia washing is carried out and silicon dioxide 15 is deposited on the surface of the structure by pyrolysis of monosilane in oxygen in the presence of a temperature. A phosphorosilicate glass with a 6-8% phosphorus content is formed. Film thickness is on the order of 1.0-1.2 microns.

After hydromechanical removal in deionized water is carried out

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phosphorosilicate glass by thermal method. The deposition is carried out under the same conditions as the diffusion of phosphorus, only time is changed.

Then, using photolithography, the contacts are opened, aluminum 16 is sprayed by the method of evaporation in vacuum, 1.2 µm thick, heat treated at 450 ° C, in medium Ar for 15 min, photolithography is formed by drawing, aluminum 16 is etched in a picker of composition HjPO rHNOj: SNSOD 140: 6: 30: 5 for 20-30 minutes, remove the photoresist in a mixture of mono-ethanol and dimethylformamide in a ratio of 1: 2, wash in deionized water for 10-13 minutes and cause firing at 480s in for 15 minutes in the medium Ar,

Claims (1)

METHOD FOR PRODUCING LARGE INTEGRAL CIRCUITS ON MIS TRANSITORS, including gate oxidation of a silicon substrate, deposition of a silicon nitride layer, formation of a protective mask, ion doping of inactive regions, etching of silicon nitride from them, local oxidation of these regions, etching of silicon nitride regions, etching of silicon nitride regions polysilicon, the formation of polysilicon gates and interconnects, the removal of primary oxide from the areas of runoff and source, the diffusion of impurities in them and polysilicon sites, application acidic silicon by pyrolysis, opening contact pads and subsequent metallisation, characterized i in that, in order to increase the output circuits of suitable process before the step of applying a layer of silicon nitride in the initial oxide layer is opened contact windows for subsequent contacting polysilicon to silicon. FIG. 610049 ^ha OS