SU667969A1

SU667969A1 - Device for testing units of electronic computers

Info

Publication number: SU667969A1
Application number: SU762373020A
Authority: SU
Inventors: Валерий Федорович Белкин; Борис Зямович Баркан; Владислав Васильевич Прошаков
Original assignee: Предприятие П/Я В-2230
Priority date: 1976-06-01
Filing date: 1976-06-01
Publication date: 1979-06-15

Description

(54) УСТРОЙСТВО ДЛЯ КОНТРОЛЯ УЗЛОВ(54) UNIT CONTROL DEVICE

ЭЛЕКТРОННЫХ ВЫЧИСЛИТЕЛЬНЫХ МАШЙЙELECTRONIC COMPUTING MASHY

Claims

The invention relates to the field of automation and computer technology and can be used in the implementation of technical means for monitoring and diagnosing malfunctions of logical nodes of discrete automation devices and electronic computers. A device for controlling electronic computer units is known comprising an input unit, a memory unit, a switch, a comparison unit, a display unit, a control unit, wherein the first input of the input unit is connected to the input of the memory unit whose output is connected to the first input of the switch, the outputs connected to the external contacts of the monitored node, the second output of the input unit is connected to the input of the control unit whose outputs are connected respectively to the control inputs of the input unit, the memory unit and the display unit connected an input with a comparison unit output, a setup register connected by an input with a first output of an input unit, a control input with an output of a control unit, an output with a second input of the Switch; the output of the memory unit is connected to the first input of the comparison unit, the second input of which is connected to the output of the switch 1. A disadvantage of the known device is that it does not provide for the control of sequences; circuits, and its diagnostic capabilities are reduced to the use of diagnostic tests only, which is associated with large preliminary costs of their development. A device for controlling digital nodes of electronic computers is known, which contains a specialized calculator, input / output devices, interface block and measurement unit.

2 A disadvantage of this device is the complexity and necessity of creating test control programs, and its diagnostic capabilities are limited to the use of diagnostic dictionaries or diagnostic control programs. The closest technical solution to the present invention is a device comprising a control unit, an arithmetic logic unit, an exchange and status register block, a 3-memory RAM block, a microprogram memory block. , first level channel, external memory block I / O unit, second level channel, bus switching unit, interface blocks, control point selection units, interrupt unit, comparison unit, checksum counter, the outputs of the control unit are connected to the control arithmetic logic unit, first level channel, second level channel, exchange register and status block, micro program memory block, main memory block, checksum counter and interrupt block, arithmetic logic block outputs an eye connected to the inputs of the control unit and the unit of registers of exchange and states, the corresponding outputs of which are connected to the inputs of the arithmetic logic unit, the first level channel, the second level channel, the bus switching unit, the main memory unit, the information outputs of the opera- tion block. The main memory is connected to the inputs of the exchange register and status block, the first level channel, the second level channel, the arithmetic logic unit and the bus switching unit, the outputs of which are connected to the inputs of the interface blocks, the outputs of the interface blocks, the outputs of the checkpoint selection blocks are connected to the inputs of the checksum counter and the comparison flea, the output of which is connected to the input of the control unit, the outputs of the microprogram memory unit are connected to the corresponding inputs of arithmetic of an optical unit and a main memory unit, the corresponding outputs and inputs of the first level channel are connected to the inputs and outputs of the external memory block, and the corresponding outputs and inputs of the second level channel are connected to the inputs and outputs of the I / O unit, interrupt request outputs of the external memory block I / O and interface blocks are connected to the inputs of the interrupt unit, the output of which is connected to the input of the control unit, the first c. The dashes of the control point selection blocks are the inputs of the device 3. The disadvantage of this device is the need for preliminary Composition 1 and control-diagnostic tests, the impossibility of using it for testing sequential circuits, and its diagnostic ones; the possibilities are connected with the use of diagnostic programs of the control and are essentially limited to diagnostics. , That is, the device has a small functionality because it does not provide for the diagnostics of sequential and combinational circuits. The aim of the invention is to extend the functionality of providing diagnostics for the sequencing and omnibration circuits irregularities. The goal is achieved by the introduction of a unit for forming standards, a block of registrars, a block for specifying a modulus, a recalculation block, a block for specifying real addresses, the outputs of the orming unit of the standards register, and the control block, block Comparison, the Transition Registrar's block, the outputs of which are connected to the inputs of the control unit, 5 Comparison Units and the Assignment Unit of the Conversion Modules / Outputs of the Assignment Unit of the Conversion Modules are connected to the corresponding inputs Comparison unit and real address setting unit, the output of which is connected to BTOptirt inputs of control point selection blocks, the corresponding inputs of the regmen and medium register block are connected to the inputs of the pattern generation unit, the transition register block and the real address setting block, the corresponding outputs of the control block and blocks Selection of control points are connected to the inputs of the unit for forming standards, the output of the checksum counter is connected to the corresponding input of the unit for specifying the conversion modules. The device provides both programmatic control and fault diagnosis. Combination and sequential circuits, as well as their monitoring and diagnostics on pseudo-random codes and in a multi-terminal system with time sharing, that is, ensures simultaneous operation of several remote control panels (interface blocks) using a standard pseudo-random cyclic code generated by the polynomial aCh) 5: aLx) x (S is the number of information input channels of the item being tested) in the checksum mode on a fixed field of pseudo-random combinations. FIG. 1 shows a block diagram of the proposed device; in fig. 2 is an example of the technical implementation of the unit for forming standards; in fig. 3 is an example of the technical implementation of the block registers transitions. The device contains a control unit 1, an arithmetic logic unit 2, a unit 3 of exchange and state registers, a unit 4 of firmware memory, a block 5 of operational memory, a channel 6 of the second level, a block 7 of input / output, a channel 8 of the first level, a block 9 external memory, trunk bus switching unit 10, interface block 11, interrupt unit 12, benchmarking unit 13, checkpoint selection block 14, checksum counter 15, block of assignment of recalculation units block 16, block of real address assignment, comparison block 18 , block 19 transition regimens, tires 20 interrupt requests Nij, bus 21 connecting cont Rui products. A unit for forming standards (see, fig. 2) consists of a register 22, a set of 23 reference elements, a switch 24, a comparison circuit 25, and a division node 26. Block 19 of the transition registers (see FIG. 3) is coded from register 27, scheme 28 compare neither modulo two, node 29, priority, decoder 30. The device works as follows. At the stage of preliminary preparation of the device for operation, it performs a series of operations on loading the operating system and the formation of service data arrays to create a model of the product under test in the formation unit 13. After switching on the device, the signal from block 1 accesses the block 4 of the memory of the microprograms and issues the sequence of load program commands to block 5 of the working memory. The information from the external memory block 9 through the channel 8 of the first level-gn is rewritten into the block 3 of the Exchange and status registers. Here, a sequence of control sets is created for setting a mode: interchange with the I / O unit 7 and the external memory unit 9, and addresses are set in the main memory unit 5, which provides control commands to the bus switching unit 10. Then, the functional model of the tested product is formed. For its formation, information on the assembly connections of the product is used, inputted via input / output unit 7. In addition, a catalog of integral circuits used in products of a checked type and information on the location of elements on the cell field is introduced to form a model. In preparation for entering the corresponding arrays into the RAM, the basic elements of the functional units are divided into conditional basic elements of the type AND OR, NOT-AND, NOT-OR. The type catalog stores information about the division of functional units into conditional basic elements and about the relations between them. When splitting, the base elements are numbered and the new values of the numbers of one-time elements and attributes are entered into the array. In block 5 of the RAM, the array of the Direct Links and the array of the Direct Links are stored, and in the t-th place: in the MacdMle Direct ™ link, the relative address of the array of direct connections, beginning with which conditional numbers are delimited by delimiters base elements, at least one input of which is associated with the output of the ith conditional base element. In addition, an array of backlinks and an array of feedbacks are formed, similar to the two previous arrays with the replacement of inputs to outputs. Obtaining opium arrays is as follows. When splitting into conditional basic elements and their numbering, the information in the directory of types of microcircuits about direct connections between conditional basic elements inside functional elements is entered into arrays of direct links and direct connections. Then all the conditional basic elements are considered, the information of which has not yet been included in the masses. The output coordinates of the base item being processed are entered in the first free cell of the direct link array. After entering all of the listed information from I / O unit 7, the specific device of which is determined by channel 6 of the second level, controlled by registers of block 3, the information on the registers after the necessary calculations and data conversions recorded in block 9 of external memory and commuting jibix channel 8 of the first level, through the arithmetic logic unit 2 enters the block 3 of the registers of exchange and states. The order in which the data command is received is determined by the Operating System, which is loaded into block 5 of RAM. The loading of the operating system is initiated by the control unit 1, which sets the sequence of operations in accordance with. a sequence of instructions recorded in block 4 of firmware memory, which is a sequential memory. In accordance with the model of the monitored cell formed in the pattern-forming unit 13, the array of states of all basic elements f of the cell being tested is determined at each control diagnostic test entered through the channel 6 of the second level from block 7. input directly from the memory unit 5. The mode of entering test information is determined by the operating system. -At the stage of program control of logical nodes with 11 conjugation blocks, -the control terminal blocks to which it is under. When items are monitored in a controlled manner, the signal for interrupt requests on bus 20 is generated. These signals are sent to the interrupt block l2, where they are processed and, in accordance with the service discipline specified by the operating system, are received as requests to the control block 1. One of the blocks 11 is connected via block 10 to an exchange channel with block 5. From the connected unit 11 information about the type of products being tested and the mode is indicated. control Through the busbar switching unit 10 via the selector control buses, this information arrives at block 1, where it is decided to issue the appropriate control commands determined by the operating system specified from block 5. After the signals are issued, the C71 of auxiliary and auxiliary signals, determined by the specifics of the products being tested, is issued a test that separates the inputs and outputs of the monitored product. Then, a sequence of setup kits is issued, and the task of test-diagnostic stimulation kits is carried out. The response of the controlled product is recorded in block 5 and, as it accumulates, enters the arithmetic logic unit 2, where real and reference states of the controlled product are compared, the COOTs do not have the specified stimulating effects. When a discrepancy between the actual signals at the outputs of the monitored product and the reference ones is detected, the monitoring set, on which the mismatch occurred, enters the register 22 of the standard setting unit 1 through the unit 3 of the exchange and status registers, and the switch 24 receives the code corresponding to the connections) element from the set of reference elements 23, the type of which is acc. There is an element at the output of which the signal did not match the reference value. Previously prepared arrays by the contact number at which this mismatch occurred are used to determine the address of the element,. . connected to the output with this contact, and through the Christmas tree of the 3 exchange registers and states, the address is entered into block 17 of the assignment of real addresses, which modifies this gap. , from the model code of the node to the real address of the element on the cell. From block 17, a code is issued to control the block 14 of selection of control points, which, in correspondence with a given address, connects the leads of the element (inputs and outputs) to the block 18 of comparison. The other inputs of block 18 receive signals from the terminals of an electronic element from a set of 23 reference elements connected to a FiBuTSb-WSuiSc switchboard - ISsibii. -i rum 24. The signal from the output of block 18 makes a decision about the health of the checked element, and in the case of coincidence of the signals at the terminals of the reference and monitored element from block 1, a signal is transmitted to calculate the address of the next element associated with one of the inputs of the element checked at the considered stage. At the same time, a risk assessment of critical conditions is made on the set of stimulating effects under consideration. To do this, the previous control set is written to register 27 of block 19 of the transition registers, and at input c. modulo-two comparisons 28 are given to the monitoring set, in which the first discrepancy between the output and reference states is obtained. Taking into account possible maximum delay spreads, control signals are selected at priority node 29. With the occurrence of signals at the outputs of the decoder 30, which performs the convolution of the code in-polyadic, the possibility of the occurrence of critical contests is determined. In this case, the monitoring set is discarded - and broken down into a set of sets in which the stimulating effects can be changed at more than one input of the controlled node. In this case, the modulo-three comparison circuit 25 and the division nodes 26 of the pattern forming unit 13 are used to determine the state fields. After checking the entire set of elements, a pair of elements will be determined for which the output (input) signals do not correspond to the set. reference sets. The use of blocks 13 and 19 ensures that the device operates in this mode to control and find the fault location for combinational circuits as well. and schemes with an arbitrary number of memory ranks. The software control mode of the logical nodes is associated with the high cost of pre-disassembling the control and diagnostic tests and can be effectively applied only to fixed batch production. In the case of pilot production, this method of control is associated with even higher costs due to the large number of adjustments in the documentation development process. Therefore, in the proposed device provides for the control of nodes on pseudo-random codes. The known control devices do not allow the diagnosis of failures using these methods and the control of sequential circuits. In the mode of monitoring and diagnostics of faults and pseudo-random codes, as well as in the program mode, preliminary recording of service arrays and alternate connection of the interface units 11 to the main buses of the device is carried out. The corresponding signal separates the inputs and outputs of the monitored product and generates a sequence of installation kits and constant control signals. The arithmetic logic unit 2 is transferred by the control unit 1 to the pseudo-random code generation mode generated by the polynomial K-1 (-oi (i) r ajfxVK de n - the number of information input channels of the item being tested, a- (x) xrTjod (x) moreover, gfx) is an arbitrary polynomial with coefficients from a field GP (Four g. “In this case, a pseudo-random cyclic code with a code distance equal to one enters black trunk buses to the inputs of the connected interface unit 11. The generated sequence of pseudo-random codes is entered into memory block 5 and with the rate of operation of this block, and is output to the bus lines. At this stage, the code is rewritten into the external memory block 9 via the first level channel 8 and can be used multiple times for testing products with a number of endpoints not less. Stimulating test patterns in the form of pseudo-random codes and constants control signals that determine the discontinuity of feedbacks in. controllable products and interdependent. the input actions, which ensure the exclusion of prohibited stimulation sets at the inputs of the controlled product, unambiguously determine the sequence of fields of the state of the elements of the controlled product. At the control stage on pseudo-random test suites, the total checksum and output tires of the controlled product are determined with the help of the 15 checksum counter. The calculated checksum is recorded in the RAM block 5 and supplied. in block 16, the assignment of the recalculation modules, where the conversion is performed, which consists in the successive division into coefficients c. j (x). From the output of block 16, the code is fed to the input of the comparison unit 18, to the other inputs of which the reference checksums are set from the block of 3 exchange registers and states. Moreover, the reference checksum can be either calculated with the help of the model of the product under test, or determined by monitoring a known good. an item. When co-coded by the coda at the inputs of block 18, the controlled product is recognized as operable. If the total checksum did not match the reference, then the local checksums for each output are calculated. These checksums are compared with their reference values and the first, for example, in order of increasing contact numbers of outputs of the monitored product, the control value that does not coincide with the reference one, determines the address of the element associated with the output contact, on. which there was a mismatch of checksums. Using the checkpoint selection block 14 at the address determined by the block 17 for specifying real addresses, the element outputs are connected to the checksum counter and the checksums are compared with the reference values. At the same time, the switch 24 of the pattern forming unit 13 connects the inputs of the reference element to the inputs of the element located in the tested Product. The outputs of the reference and controlled elements are connected to the input. ladies block 18 comparison. The control is repeated on the full pseudo-random set. and when the signals of the outputs of the elements coincide, the decision is made about the health of the element installed in the product. Using the arrays of links and references, the address of the next element associated with the element checked at the previous stage is determined. The procedure is completely repeated. Upon detection of the first element, the functioning of which does not coincide with the functioning of the reference element, a pair of possibly faulty elements is formed. Separation. The malfunction is performed by one of the known manual methods. The use in the proposed device of the unit 13 for forming the standards of the unit 19 of the transition registers and the unit 16 for assigning the modules of recalculation provides control and diagnostics of malfunctions of combinational and sequential circuits not only in the program control mode but also using pseudo-random sets. This is especially effective at the stage of production of prototypes of products, when the structure of controlled products undergoes considerable processing and the development of control and diagnostic tests is associated with significant labor and machine time, as well. Operative adjustment of tests is difficult. Compared with the known devices, the proposed method possesses greater functionality, since it provides control and finding fault locations for arbitrary types of logical nodes, including sequential circuits with an arbitrary number of Russ and constant zero and constant unit faults, combining arbitrary circuits. . Claims An apparatus for monitoring electronic computer units comprising a control unit, an arithmetic logic unit, a peffifdtpOB exchange and state block, an operational memory block, a microprogram memory block, a first level channel, an I / O block, an external memory block , channel of the second level, switching unit. . trunk buses, interface blocks, control point selection blocks, interrupt unit, comparison unit, checksum counter, the outputs of the control unit are connected to the control inputs of the first level channel arithmetic logic unit, the second level channel, and unit, microprogram memory, memory block, check sum and block counter; arithmetic logic blocks are connected to the control unit and exchange register and status block inputs, the corresponding outputs of which are connected to the inputs of logical block arithmetic, first level channel, second level channel, bus switching unit, operational memory unit The information outputs of the operative memory block are connected to the inputs of the block. exchange registers and states, kana. the first level, the second level channel, the arithmetic logic unit and the bus switching unit, the outputs of which are connected to the inputs of the interface units, the outputs of the interface units are the device outputs, the outputs of the control point selection blocks are connected to the checksum input and the comparison unit, the output of which is inertial with the input of the control unit, the outputs of the microprogram memory unit, is compatible with the corresponding inputs of the arithmetic logic unit and the memory location, the corresponding outputs and inputs of the channel are The voltages are connected to the inputs and outputs of the external memory unit, and the corresponding outputs and inputs of the second level channel are connected to the inputs and outputs of the I / O unit, the interrupt request outputs of the external memory unit, the I / O unit, and the interface units are connected to the input of the unit interrupts, the output of which is connected to the input of the control unit, the first inputs of the control point selection units are the device inputs,. This is due to the fact that, in order to expand the functionality by providing diagnostics of sequential and combinational circuits, the device includes a unit for forming standards, a block of transition registers, a block for setting recalculation modules, a block for specifying real addresses, and the outputs of the standards generation unit are connected to the corresponding inputs of the exchange registers and states block, the control block, the comparison block, the junction block, whose outputs are connected to the inputs of the control block, the compared block and a block of assignment of recalculation modules, the outputs of a block of assignment of recalculation modules are connected to the corresponding inputs of the comparison block and the registers block, the output of which is connected to the second inputs of the selection block, control points, the corresponding inputs of the block of exchange registers and states , a block of transition registers and a block for specifying real addresses, the corresponding outputs of the control block and blocks for selecting control points are connected to the inputs of the shaping unit. standards, the output of the checksum counter is connected to the corresponding input of the task block of the conversion modules. Sources of information taken into account in the examination 1, USSR Copyright Certificate 498619, cl. G 06 F 11/00, 1974. 2, eeectronics 21, 1972w. u. AeSam Litep rcfted mstfument set up test intfiv cate orssembEies p. f. 104-109. 3, USSR Author's Certificate No. 469971, cl. G 06 F 11/00, 1973.

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