SU657433A1 - Information shifting arrangement - Google Patents

Description

The invention of fire ogosigs to automagics and computational techniques can be used in devices for shifting numbers. A device for shifting information is known, which contains a shift register in which numbers are shifted, shift control nodes l. The disadvantage of such devices & low speed, as in these devices the shift of the number by N bits is carried out aa-N cycles. For large N, the time it takes to perform a shift operation in such devices is large. The closest in technical terms to the claimed is a device for shifting numbers, containing a reversible shift register, two AND elements, a reversible counter, two comparison circuits and a control unit, with the output of the lower reversing shift register connected to the first the input of the first, and Ы) 1 input of the higher discharge .- to the first input of the second element I, the output of the first element I connected to the input of the older one, and the output of the second element I to the input of the lower discharge reversing shift offset, the installation inputs of the reversible counter and the inputs of the first comparison circuit are connected to the information inputs of the device, the outputs of the reversible counter are connected to the inputs of the second comparison circuit, the outputs of the comparison circuits - to the inputs of the control unit, the outputs of which are connected to the corresponding controls of the reversible shift register 2 and reversible counter 2. However This device may have additional information after performing the shift operation, which distorts the accuracy of the result of the operation. The aim of the invention is to increase the reliability of information shift. The goal is achieved by the introduction of a shift register, the setup input of which is connected to the output of the first comparison circuit, and the control inputs to the corresponding EE4 control inputs of the reverse shift register and the output of the first comparison circuit, the output of the low-order additional reverse register is connected to the second the first entry, the output of the older bit. to the second input of the second element, And, and the outputs of the bits of the additional shift register are connected to the inputs of setting the zero of the same name bits of the reversible shift register. The drawing shows a diagram of the device. The device contains a reverse shift register 1, elements 2, 3, shift register 4, control unit 5, comparison circuits 6, 7, reversible counter 8. The low-order output of the reverse register 1 from 1 through element 2 is turned on to the input of the high bit, and the output of the high bit through the element 3 And is connected to the input of the lower bit. Shift control inputs of the reverse shift register 1 and shift register 4 are connected respectively to the first and second outputs of control unit 5, the third and fourth outputs of which are connected to the addition and subtraction inputs of the reverse lock 8, respectively. The output of the reverse lock pin 8 is connected. to the input of the comparison circuit 6, the output of which is connected to the first input of the control unit 5 and with the control input to the reading of the shift register 4. The first output of the comparison circuit 7 is connected to the second input of the control unit 5, and the second output is connected to the installation input in the I register 4 of the shift. The outputs of the bits of the 4 shift register are connected to the installation inputs in O of the corresponding bits of the reverse shift register 1, and the high and low bits of the bits are connected to the second inputs of elements 2, 3 AND, respectively. The device works as follows. When the shift value is N € y (p. - the number of digits of the reverse shift register 1, the number shift is found. It is found in the reverse shift register 1 in the corresponding direction by a specified number of bits. When the shift value is in the reverse shift register 1, the shift is cyclic numbers in the opposite direction (as compared with a given direction of shear), while shifting is performed by (n-S) bits. After the completion of the operation of the shift in the reverse shift register 1, only those bits of the initial number that are received along the transfer chain are fixed, the remaining bits are set to O. The shift signals are generated by the 5 ynpai block. The magnitude of the shift enters the reversible counter 8 and the comparison circuit 7. 7 the comparison generates the shift direction control signals, which are fed to the control unit 5. In the reversible counter 8, the number of shifts is counted, while the reversible counter 8 is operated or subtracted (N4-9-for addition (LJ-), the addition and subtraction signals come from control unit 5. The end of the shift operation is fixed by the circuit 6 comparisons in the zero state of the reversible counter 8, or when its state is equal to P. Shift register 4 is used to fix the result of the shift and to control the elements 2, 3 AND during the cyclic shift. compare Not all the bits of the shift register are set to 1. The shift signals entering the reverse shift register 1 simultaneously arrive at the shift control in the shift register 4. The code in the shift register 4 is shifted by the same amount of bits and in the same direction as the number in the reverse shift register 1. Since the shift in shift register 4 is not cyclic, after the end of the shift (nN) the bits in it will have a zero value: when shifting to the left (nN), the lower bits, when shifting BnpaBo (ii-N) older bits After the end of the shift by the signal from the comparison circuit 6, the contents of the shift register 4 are read and, as a result, the (and-N) bits of the reverse shift register 1 retain their values, and the rest are set to Cf by signals from the outputs of the bits of the register 4 shear. Signals from the outputs of the high and low rads (overflow signals) are used to control elements 2, 3 and in the transfer chains of the reversible register 1. shear. With a shift value of - -, all bits of the shift register 4 have a zero value (they are not set before the shift) and therefore reading the contents of shift register 4 at the end of the operation does not distort the result of the operation in the reverse shift register 1.

Consider the operation of the proposed device by the example of a shift of the number 1O11.O1110OI left and right by 4 and 9 bits. The results of the shift operation and the state of the reverse shift register 1 and shift register 4 after the operation is performed are shown in the table. When shifting left and right by 4 bits (examples 1, 2), the

the numbers in the reverse shift register 1, in the shift register 4, all bits are set to 0 and the result of the operation is not affected. When shifting to the right by 9 rads, the cyclic shift to the left by 3 bits is performed, while the older bits are released along the cyclic transfer chain (through the element I 3) are fed to the input of the lower bits.

The code in shift register 4 is shifted by 3 bits to the left, the lower three bits after the operation are set to O, the remaining bits will be written. After reading the contents of register 4 shifts in the reverse shift register 1, three lower bits are stored, the older nine bits will be set to O, which corresponds to a shift of the original number by 9 bits to the right. When shifting by 9 bits, the contents of the reverse shift register 1 are shifted by three bits to the right, the lower bits are released through item 2, and are fed to the input of the higher bits. In shift register 4, after the end of the shift, the three most significant bits are set to O, and nine bits are set to. After reading the contents of the re

Gisgra 4 shifts in the reverse shift register 1 only three high-order bits are saved, which corresponds to a shift of the initial number by 9 bits to the left.

Thus, in the proposed device, the initial number can be shifted to any number of bits in either direction, with the maximum time for performing the iteration does not exceed ticks, where n is the difference of the reverse shift register 1.

Claims (2)

1.Bukreev, I.N., et al. Microwave, Digital device digital circuits., Owls, Radio, 1975, p. 139, fig. 4.10. 2. USSR author's certificate No. 382146, class, C 19/00, 1971.