SU656109A1 - Storage unit checking device - Google Patents

Description

The invention relates to the field of storage devices.

One of the known devices for monitoring memory blocks contains an address generation unit connected to the address inputs of a checked memory block, a comparison block connected to the output of the memory block being checked and a numeric write bus, an error fixing block connected to the comparison block, and a control unit connected to the readable memory block by the read and write control buses as well as the numeric write bus 1.

A disadvantage of this device is that it does not provide for the acquisition of one-bit memory blocks with defects for combining them into full-sized memory blocks with error correction.

Of the known devices, the closest in technical solution to this invention is a device for monitoring memory blocks, comprising a series-connected comparison unit, a control unit and a registration unit, one of whose outputs is connected to the control input of the memory unit, element And, the inputs of which are connected to the outputs of the comparison unit and the memory unit, and the output - to the input of the registration unit, the address generation unit, one of the inputs of which is connected to the first output of the control unit, and the output - to the output of the device 2.

In this device, the control and acquisition of one-bit memory blocks with defects in a full-size memory device with error correction is performed under the condition that there should be no more than 1 error at each address of the full-size memory device. In this device, the memory block consists of two blocks. In this case, information about defects of the checked memory block is stored in the first memory block, and information about defects of already selected memory blocks for this set is stored in the second memory block. If there is no error in the checked memory block at any address, it is written to this address in the first memory block, "O, and if an error occurs at that address, it is recorded accordingly." At the same time, the same address is used to read information from

the second memory block and is fed to the input of the element I, to the second input of which a signal is fed from the checked memory block. If there is an error at any address in the checked memory block and in one of the previously checked and picked up memory blocks, then the registration block is excited, and the checked single-bit memory block is considered "unsuitable for this set. If the checked memory block is valid, then when re-searching the addresses, information is read from the first memory block and this information is written to the second memory block only at those addresses that had an error in the checked memory block.

Thus, the disadvantage of this device is the need to store information about the errors of the monitored memory block and the error information of selected memory blocks for this full-size set in two additional memory blocks, which complicates the device and reduces its reliability.

The purpose of the present invention is to simplify the device for monitoring memory blocks and increase its reliability.

The goal is achieved in that the device contains groups of AND elements and OR elements whose outputs are connected to the address inputs of the memory block, AND elements of the first group are connected to the outputs of the comparison unit and the address generation unit and the second output of the control unit, the inputs of the AND elements of the second group are connected to the output of the address generation unit and the third output of the control unit, the outputs of the elements And of both groups are connected to the inputs of the OR elements, the other output of the registration block is connected to the input of the control unit and another they input address generating unit.

The block diagram of the device shown in the drawing.

A device for monitoring memory blocks comprises a control unit 1, a comparison unit 2 ,. connected to a verifiable memory block 3, an address generation unit 4, a control unit 5, a registration unit 6, a memory unit 7, an AND 8 logical element, two groups of AND 9 and 10 elements, respectively, OR 11 elements.

One of the inputs of block 4 is connected to the first output of block 1. The outputs of the elements OR 11 are connected to the address inputs of block 7, the inputs of elements AND of the first group 9 are connected to the outputs of the comparison block 2 and block 4 and the second output of block 1. The inputs of the elements AND the second group 10 connected to the output of block 4 and the third output of block 1. The outputs of the elements 9 and 10 are connected to the inputs of the elec- tants OR 11. One of the outputs of block 6 is connected to the control 6565109

mu input block 7, the other output - to the input of block 1 and the inputs of block 4.

The principle of operation of the device is as follows.

5 Before starting the monitoring and picking of the checked memory blocks, it is preliminarily written "O to the memory block 7 at all addresses, after which the forming unit of the addresses 4 is set to" O d (the preliminary zero circuits are not shown in the drawing).

When the device is started up, the address forming unit 4 generates signals providing the enumeration of all the addresses of the checked memory block 3 and the memory block 7. 5 At the first search of the addresses, the control unit 1 generates a signal that opens the AND 10 elements, so that the address inputs of the checked block 3 and memory block 7 are turned on in parallel. At the same time, the control unit generates number pulses on the numeric write buses, the corresponding write "1 and" О for each address of the checked memory block 3, and on the control write write buses - the corresponding write and read pulses.

If an error (defect) in the checked memory block 3 is detected at any address from the comparison block 2, the signal goes to the control unit 5, which generates a signal that energizes the recording unit 6 if the number of errors exceeds a certain number. In this case, the checked memory block is considered "unusable and rejected.

If the number of errors was less than the specified value, then a signal from the recording unit 6 is sent to the input of the memory block 7, which leads to reading information from the memory block 7 at the same address.

The read signal from the memory block 7 is fed to the input of the AND element 8, to another input of which the signal from the comparison block 2 arrives. If there is an error in the checked memory block 3 and reading "1 from memory block 7 (which corresponds to the presence of a defect in This address in one of the 5 previously selected memory blocks for this full-size set of memory blocks, element E.8 produces a signal that excites the recording unit 6, and the checked memory block 3 is considered "unsuitable for this set of full-sized memory blocks and is deposited in m assisting one-bit memory blocks that will be involved in picking the following full-size memory blocks.

If the tested memory block 3 is "usable for this set of full-size storage devices, then the recording unit 6 generates a signal that excites the address generation unit 4 and the control unit 1, which generates a signal leading to locking the AND 10 elements and opening the elements AND 9. Through the group of elements AND 9 and element OR 11 to the address inputs of the memory block 7, the address code from the address generation block 4 gets only if the comparison block 2 detects an error (defective storage element) in the wire The memory unit 3 is being detected. Simultaneously from the recording unit 6, a signal is received leading to the entry "1" at this address in the memory unit 7.

The described device for controlling memory blocks allows the device to be significantly simplified by eliminating expensive equipment.

Claims (2)

1. USSR author's certificate number 341687, cl. G 11 C 29/00, 1971. 2. For the number 2345189/24, cl. G 11 C 29/00, 1976, according to which the positive is accepted 5 decision on issuing copyright certificate.