SU1674269A1 - Main memory unit with error correction - Google Patents

Abstract

The invention relates to computing and can be used to build testable storage devices with error detection and correction tools. The aim of the invention is to simplify the control of the device. The device contains primary and secondary drives, output and control code registers, a comparison unit, an error correction unit, a control bits generator, input and output signal drivers, a mode register, and the first and second multiplexers. The purpose of the invention is achieved by introducing a mode register and multiplexers that, in software mode, provide access to test bits for writing and reading, as well as simulating errors by separately writing to the primary and secondary drives. 1 il.

Description

The invention relates to digital computing, namely, RAM, which contains means for monitoring the accuracy and error correction of stored information and intended for use in highly reliable digital computing systems.

The aim of the invention is to simplify the control of the device.

The drawing shows a structural diagram of the RAM with error correction.

The error-correcting RAM contains shapers of 1 input and 2 output signals, primary 3 and additional L drives, shaper 5 control code, trigger b mode, multiplexers 7 and 8, output register 9, register 10

control code, as well as block 11 comparison and block 12 error correction

The RAM operates in several modes, which are specified by the state of the register / register 6 mode. The setting of various states of the outputs 13-17 of the mode register 6 is carried out by writing to it via the information highway of the binary control layer, in which a certain state of each bit corresponds to a certain state of one of the outputs of the register.

When testing RAM, only five of all possible modes are used.

At the beginning of work on the control line, an initialization signal is sent to the RAM, as a result of which at all outputs of register 6 of the mode is set

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logical zero, which corresponds to the transfer of RAM to mode 1.

The first mode is the operating mode of the RAM. The error correction prohibit input of the error correction block 12, the control inputs of multiplexers 7 and 8, the prohibition entries for recording the primary and additional 4 accumulators receive logical zero signals, which corresponds to the resolution of error correction by block 12, transmission of information from the outputs of the imager 5 multiplexer 7 and information from the information outputs of the block 12 to the multiplexer 8 and the recording resolution in both storage units 3 and 4. When recording in the first mode, the information coming through the imager 1 of the input signals from the information the main line, is written to the main drive 3, and its control code, generated by the generator 5, is written to the additional drive 4, arriving at its information inputs through a multiplexer 7. When reading the information read from the main drive 3, through the register 9, the output The data is fed to the information inputs of the error correction block 12. At the same time, the shaper 5 generates the control code of this information, which is fed to one of the inputs of the comparison unit 11. The other inputs of the comparison unit 11, through the control code register 10, receive a control code read from the additional accumulator 4. If the indicated codes are equal, the output of the error comparison block 11 forms a sign of no error, which goes to the error sign inputs of the error correction block 12.

The information read from the main accumulator 3 is transmitted unchanged to the output of block 12, and then through the multiplexer 8 and shaper 2 of the output signals is output to the information highway. At the same time, from the output of the error indication of the error correction block 12, a signal of the absence of an error is output to the control highway.

In the case of the difference between the codes arriving at the inputs of the comparator unit 11, the latter forms an error indication, which arrives at the inputs of the error indication of the error correction unit 12. On the basis of this feature, in block 12, this error is corrected in the information received at the information inputs of block 12, after which, through multiplexer 8, the output driver 2 is output to the information line simultaneously with the no-error signal received

to the control highway from the control outputs of block 12, and in the case of an unrecoverable error from the output of block 12 through multiplexer 8 and the driver 2 to the information highway, unspecified information is output simultaneously with the signal of an unrecoverable error coming to the control highway from the output of the error sign of block 12.

The second mode is designed to check the main drive 3 and register 9 output data. The second mode differs from the first mode by applying a signal of a logical unit to the input of the error correction error of the device of the error correction block 12, which corresponds to the error correction error block 12.

Recording in the second mode is similar to recording in the first mode. When reading, the information read out from the main storage unit 3 is transmitted without change through the error correction unit 12, the multiplexer 8 and the output signal generator 2 to the information highway. Thus, in the second mode, errors occurring in the main drive 3 or output register 9 are detected by blocks connected to the same address, control, and information lines as the described RAM by comparing the information read from the RAM with the previously written into it. .

Since the information stored in the additional memory 4 does not affect the information read on the RAM, the state of the outputs 14 and 17 of the register 6 of the mode does not matter.

The third mode is designed to test the additional accumulator 4 and the control code register 10 and differs from the first mode by supplying the logic unit signals to the control inputs of multiplexers 7 and 8, which corresponds to the transmission of information by multiplexer 7 from the output driver 1 of the output signals, and by multiplexer 8 from the outputs register 10 control code.

When recording in the third mode, the information received through the shaper 1 of the input signals and the multiplexer 7 from the information highway to the information inputs of the additional storage device 4 is recorded in the storage device 4.

When reading, information is read from the additional storage device 4 through the control code register 10, the multiplexer 8 and the output signal generator 2 is fed to the information highway.

Thus, in the third mode, it is possible to check the additional accumulator 4 Enapo ically check the primary accumulator 3 in the second mode. Since the information stored in the accumulator 3. does not affect the information on the RAM, the output of 13 and 16 regisgra 6 mode is not known.

The fourth mode is intended to check the driver of 5 control bits with the serviceable additional drive 4 and register 10 of the control code. The fourth mode differs from the psi mode by applying a signal of a logical unit to the control input / i., Of the hypoxplex 8, which corresponds to the transmission, i.e.

Recording on Thursday mode is similar to recording in the first mode. When reading the information read from the additional storage A., which is the control code of the previously recorded (RAM information, provided that the recording was performed in the fourth mode, through the register of 10 control bits, the multiplexer 8 and shaper 2 output signals are transmitted {yurmatsionnaya highway.

Thus, in the fourth mode, it is possible to check the control code generator 5 by checking the correctness of the control codes read from the RAM corresponding to the previously recorded information. Since the information stored in the main drive 3 does not affect the information read out of the RAM, the state of the outputs 13 and 16 of the mode register b does not matter.

The fifth mode is intended to check the block 11 comparison code b while 12 error correction with repair i / main 3 and additional 4 accumulators, as well as the control code generator 5 and includes modes Va and V6. The Va mode is otlioetsya or the first signal of the logical unit to the input of the prohibition of recording additional storage L, and mode V6 - by applying a signal of the logical unit to the input of the recording of the recording of the main storage 3, which corresponds to the prohibition of writing to the drive h (mode Va) and to drive 3 V6). Writing to the primary storage device 3 in the Va mode and to the additional storage device 4 in the V6 mode is similar to the corresponding actions in the first mode. The difference from the first mode is that when recording in modes Va and V6, the information previously stored in additional drive 4 (for mode Va) and main drive 3 (for mode V6) is saved in% i / s At 6 ai p n IHU reading in the first roh ip By the mdstl tg-pnu perform the recording first and r-ghmr Va then and mode V6 pozg tpchet

separately write ich} prmatsch about ts os ti cm my drive 3, and c from the notes i HV- shch and control code in addition, l.chiy accumulate / l V

Thus, it is possible to simulate errors either about proxy information from the main control group, or in the corresponding control code stored in the additional accumulator. -one.

5When reading both in Va mode and in

In the V6 mode, the errors carried during the recording are corrected in the case of healthy blocks of 11 cf. pnoni codes and block error correction. The presence of errors is information,

0 tests in my mode from RAM pl - Cit h due to failures of the indicated blocks 1 I and 1. Checking RAM in this mode will result in checking the error correction in the information stored in the nt & 3, and

5 check that the error in the control code, stored in drive 4, is not affecting the reliability of the read- ing media read from RAM.

Error correction ram can

0 also use the quality of RAM Oz error correction with an increased memory obbt.ma due to additional information about the accumulator L for storing ics memory recorded in RAM on in5 (J orms of the OUT backbone P case of odmi-copy of the digit main 3 and additional 4 drives it is possible to get RAM with double memory obgem

0At the same time at any time

Only one of the drives 3, 4 will be able to access the main trunk, which is determined by the state of the outputs of the register 6 of the mode.

5 For organizing work 03 / without error correction with an increased memory capacity, two modes are used. The sixth mode is intended for accessing information storage to the main storage device 3. The sixth mode differs from the first mode by supplying signals of the logical unit nz one and the error correction block of the error correction block 12 and input of the prohibition of recording additional storage device 4 prohibits the prohibition of error correction by block 12 and the prohibition of writing to the additional drive 4.

When writing information from the information highway into RAM, it is written to the main drive 3 in the same way as in the first mode. Reading the RAM in the sixth mode is similar to reading in the second mode.

Thus, the RAM operates in the sixth mode, as RAM without error correction with the main drive 3. The information stored in the additional drive A is not destroyed. Since there is no write to additional drive 4, the output state 14 of register 6 of the mode does not matter.

The seventh mode is designed to provide access to the information highway to the additional storage device4. Compared to the first mode, the seventh mode differs by supplying logical unit signals to the control inputs of multiplexers 7.8, as well as to the recording prohibition input of the main storage unit 3, which corresponds to the resolution of information transmission by multiplexer 7 from the output of the imager 1 input signals, and the multiplexer 8 - from register outputs 10 test bits and prohibit writing to the main drive 3. Writing to RAM in the seventh mode is similar to recording in the third mode. The difference from the third mode is in the mandatory prohibition of writing to the main drive 3.

Thus, in the seventh mode, the RAM operates as RAM without error correction with an additional drive 4. The information stored in the main drive 3 is not destroyed.

Since the information stored in the main storage 3 does not affect the information read from the RAM, the output state 13 of the register 6 of the mode does not matter.

By introducing multiplexers and managing separate recordings to the drives, as well as the ability to prohibit error correction in the device, it is possible to access the contents of both drives, and consequently, check their operability using RAM check methods without error correction, as well as check the health of the error correction circuits, which makes it possible establish the fact of failure and localize it to within a node. This increases the maintainability of the device. Reliable diagnostics allows detecting failures in all the RAM nodes and, thus, distinguishing the state of the device malfunction from the operating state.

Using only serviceable RAM in operation makes it possible to consider their fault tolerance equal to the calculated one for serviceable devices, which is higher than the operability of the devices.

Claims (1)

Invention Formula Random access memory with error correction, containing the primary and secondary drives, the address inputs and write / read inputs of which are of the same name. devices, and the outputs are connected to the inputs of the output data register and the control code register, respectively, the outputs of which are connected to the inputs of the first group, respectively, of the error correction block and the comparison unit, the information inputs of the main accumulator are connected to the outputs of the output data register, to the inputs of the control code generator and to the outputs of the input signal drivers, the inputs which are connected to the outputs of the output drivers and are informational inputs and outputs of the device, the inputs of the second group of the error correction block are connected to the outputs a comparison unit, the inputs of the second group of which are connected to the outputs of the control code generator, and the error indication output of the error correction block is the output of the error indication of the device, characterized in that, in order to increase the reliability of the device, a mode register, first and second multiplexers are entered into it, and the sample inputs and information inputs of the mode register connected to one of the address inputs of the device and to the outputs of the input drivers, the outputs of the mode register one through five are connected respectively to the control inputs of the first and second multiplexer error correction blocks and to the prohibition inputs of the primary and secondary drives, the information inputs of the first and the second groups of the first multiplexer are connected respectively to the outputs of the control code generator and to one of the outputs of the input signal drivers, the outputs of the first multiplexer connected to the information inputs additional storage device, information inputs of the first and second groups of the second multiplexer are connected respectively to the outputs of the group of the error correction block and to the outputs of the control register code, the outputs of the second multiplexer are connected to the inputs of the output drivers, the synchronous input of the mode register is connected to the write-read input of the device.