SU647742A1 - Magnetic rapid-access storage - Google Patents

Description

The disadvantage of such a wedging device is a decrease in its reliability when exchanging words of small magnitude, as well as the impossibility of an arbitrary increase in dardarity

the words.

The purpose of the present invention is to expand the field of application of the device.

This goal is achieved by the fact that the selection unit of the coordinate formers, the block for the selection of bit formers, additional switches and an additional word register, whose inputs are connected to the outputs of additional switches, whose inputs of the 1 to the corresponding outputs of the amplifier selector and the inputs of the choice of bit formers, the outputs of which are connected to the inputs of the bit formers, and the inputs of the blocks for selecting the coordinate formers are connected to otvetstvuk PWM output; the register of the address and the rewriting block, and the outputs are connected with Bxt dam co-lined formers.

Such a device allows you to process only the selected area of the drive and bring the size of the word DoK8 to be processed, where M is the drive size, and ai is the number of

In Fig. 1, the structure of a memory device is illustrated in FIG. - electric storage circuit. The storage device (Fig. 1) contains a register 1 of address V, a coordinate decoder 2Y, formed 3 address current Y, a register 4 addresses X, an overwrite block 5, a bpok 6 selection of coordinate formers X, coordinate 7 (address current X), accumulator 81 (performed on the cores), amplifiers 9, block 10 Amplifier amplifiers, switches, Nothing else, switches 12 ,. registers of words 13 and an additional register of words 14, the block for selecting low-cost formers, including the primary

bit selector nodes 15 and block bit selector block 16, bit drivers 17i The device has input address bus 18, input

tires 19 addresses, input buses 2O of the census block, input tires 21 word registers, output tires 22 re.

647742

gistrov words. The bulk in FIG. 1 is reflected in the knot width.

The storage device operates as follows.

In read mode, the input numbers 19, X addresses, 18 Y addresses, and 20 rewriting blocks, the device receives the address of the first word and the number of simultaneously read words. On the ocHoBaja / u address X and the number from the rewrite unit, the selection unit 6 for the formers X selects the required number of formers 7 of the address current X. HHCJTO of the connected formers of the address current X pa. but to a number of the restart block. As a result of this, in the accumulator the address currents on the coordinate o6Moiw KBKi will cause a number of cores to come to a state, the interruptions from which will follow in all eu. In the example of a chiolo at the same time, the words being processed are called two, but it can be entered in D1 to a number equal to t, when all address formers X are selected.

Based on the decoding of the address Y, one selects the desired address current shaper Y, which sets the address current iiD of the coordinate U.3 & the address current coordinate of the coordinate Y, to be sufficient for the disappearance of the roll-over disturbances. As a result of the prokhon of any address current, information will be read from the cores selected for the two coordinates.

The amplifier selection block 10 on the register contents 4, 1 addresses X and Y connects the amplifiers associated with the bit winding, hc cut commutator 11. to register the words, and the amplifiers associated with the bit windings through the additional coke mutator, to the additional register , the words. Similarly, plug-in and subsequent amplifiers when reading three or more layers at the same time. In figure 1, 2 shows the nodes and chains only for liByx words. Thus, read as a result of cooling the address currents on co-windings, the first word will go to the inputs of the switches and, after amplification through the switch of amplifiers, into the word register. The address of this word will match the address entered in registers 4, 1 of address, X and Y. The 5 result of the npoxoafrDeni address currents along the coordinate 5 6 windings is read. The second word will go to the inputs of the amplifiers and, after amplification through an additional switchboard, the dumb register of the word will be added to the additional junction. Similarly, information will be entered in subsequent additional registers of the word ,, if a specified number is simultaneously processed & words more e) wooh. In the regeneration or recording mode, the old information of the word registers or new, stored through the input buses of the 21 word registers, will be written into the previously readable drive memory as follows. The ip block of choice of amplifiers based on the contents of registers 4, 1 of address X У connects the necessary elements of the primary nodes 15 of the selection of bit drivers to word registers. Based on the contents of the register of the word, the connected formers from the nervous node of the choice of bit formers will select the bit formers that are associated with the corresponding bit windings. Based on the contents of the additional register of the word, connect the elements of the primary node of the hub of the bit. . shapers and turn, the block of selection of random shapers will select bit shapers, associated with the corresponding discharge straps. Turning on the selected bitformers and forkshrrvvatel write address current U, butsug formed razraznye TOE zapvsi on the discharge windings and reverse current recording yo coordinate winding U, which will sew the necessary information into the selected cores. Thus, the device-consumer, setting the starting address and the desired number of words, can process from one to one time. In one cycle, Jibix is located at the single coordinate Y. In this case, no; You must read the words that were not selected by the sending device. This increases the reliability of the device and extends its field of application. The formula and a re shadow of Magnetic; onejuaTHBiipe is a memory device containing an address register. Outputs of which are connected via a coordinate 1st decoder and address current drivers to an accumulator, a ttepezapnsi block, an amplifier selection block, a rvgaster word, whose inputs through the switches are shared to amplifiers, are different formers, characterized in that they are enlarged from the range of areas with amplifiers, characterized in that they are enlarged from the area, they are divided by those that have, in particular, they are separated from them by area of the amplifiers, characterized in that they are enlarged from the area, they are divided by those that have, in this case, they are separated by areas with amplifiers, characterized in that they are enlarged by areas that are separated from them by area of the amplifiers, characterized in that they are enlarged areas that are separated from them by area of the amplifiers, characterized in that they are enlarged). It contains a block of selection of keo-edyannykh shaper, a block of choice of bit shaper, additional switches and an additional register of words, the inputs of which are connected 1 from the output. " Dami additional switches, the inputs of which are connected to the corresponding. The main outputs of the amplifier selection block and the inputs of the amp selector of bit shapers, the outputs of which are connected to the inputs of the ramping shapers, the inputs of the selection blocks of the coordinate shapers of the shapers and the overwriting block, and the outputs of the connectors with the inputs of coordinate shapers. Sources of confusion, taken into account during the examination 1. Issues of radio electronics. Ser.EVT, l. 6,1868, p. 3-9. 2, USSR Author's Certificate No. 526019, cl. q 11 C 11/00, 1974,

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