SU646340A1 - Retunable digital filter - Google Patents

Description

(54) DIGITAL REJECTABLE FILTER of zones, whose outputs are connected respectively to the input of the quantizing generator and to the first input of the coefficient memory. The range switching unit discretely changes the quantization frequency of the quantizing oscillator, and the external parameter meter present in the known filter changes it in parallel. This changes the position of the frequency response of the phytra on the frequency axis. In addition, with the help of interleaved ranges, weighting coefficients can be transferred to the coefficient memory (| factors recorded in advance in a memory device and defined form of frequency characteristics. In the specified file, the next values of input and output signals should be recorded in memory cells devices (memories), which at the appropriate point in time are occupied by the oldest values of the signals (already unnecessary for further digital operation). The addresses of these cells change with each new quantization period This leads to the fact that in each new type of quater, the order of memory cells changes, the contents of which are fed to the multiplication unit, which requires a relatively complicated control of the memory device operation. Moreover, when changing the quantization frequency, the signal must and the frequency of outputting the values of the signals from the storage device to the multiplication unit, which further complicates the management of the digital filter 2. The complexity of controlling the digital film necessitates the use of special nodes for controlling address distributor, which reduces the reliability of his work. The circuit of the invention is improved higher than the reliability of the filter. A gradual goal is achieved by introducing the OR elements and ring shift registers according to the number of bits of the filtered signal, the direct control inputs of each ring annular register are connected with the first and second outputs of the quantizing generator, the information input through the corresponding OR element is connected with the outputs of the ana-rjpro-digital converter and the heating adder, and the output is connected to the second input of the multiplication unit.,. the second input of the coefficient memory is connected to the second output of the quantizing oscillator. The filter circuit is shown in the drawing. The scheme includes: quantizing generator 1, analog-to-digital converter 2, ring shift registers 3, elements OR 4, block 5 of coefficient memory, multiplier 6, accumulating accumulator 7, range switching block 8, memory 9, inputs 10, 11 and exit 12. filter. The principle of the filter is in the following mode. The signal from input 11 is fed to analog-to-digital converter 2, where it is quantized in time and amplitude under the influence of the low-frequency output pulses of the quantizing oscillator 1, following the quantization frequency. From the output of the analog-to-digital converter 2, the signal passes through the elements 4 OR to the information inputs of the ring shift registers 3, where it is recorded under the influence of the same pulses of the low-frequency output of the quantizing oscillator 1. Each ring shift register 3 records one input bit. The annular shift registers 3 also store the corresponding bits of the previous values of the input and output signals, arranged in order of their arrival. During a single quantization period, the corresponding bits of all values of the input and output signals are shifted around the ring under the influence of the pulses of the high-frequency output of the quantizing oscillator 1 supplied to the control inputs of the shift registers 3. In this case, they alternately pass through the output bit of the ring shift registers 3 in this way that at the output bits of all the shift registers 3, all values of the input and output signals stored in the ring shift register are sequentially generated x 3. The ratio of the pulse frequency at the low-frequency and high-frequency outputs of the quantizing generator 1, is chosen in such a way that all

the values of the input and output signals pass through the output bits of the shift registers 3 in exactly one quantization period of the input signal.

From the output bits of the registers 3 values of the input and output signals are sent to multiplication unit 6, on the input of which the corresponding weights are synchronously received from the coefficient memory unit 5, whose operation is also synchronized to the control input by pulses of the high-frequency output of the quantizing generator 1. From the output of the block 6 product values of the input and output signals by the corresponding coefficients I enter B on the accumulator 7, where they are added together, as a result of which the next digit is formed Output signal setting. The generated value of the output signal is fed to the output of the digital filter and simultaneously bit-wisely fed to the inputs of the OR elements 4, through which it enters the information inputs of the ring shift registers 3 and writes them to the place of the oldest, which is no longer needed for further processing, output value. After that, the next cycle of operation of the digital filter starts, and the next value of the input signal is written into the ring shift registers 3 in place of the oldest value of the input signal.

Before processing the input signal, the digital filter is tuned to the required bandwidth, for which, by a signal from the range switching unit 8 to the control input of the memory device 9, weighting factors are recorded in the coefficient memory unit 5 through the range switching unit 8 from the storage device 9. In addition, a discrete switching of the frequency of the quantizing oscillator 1 is performed according to a signal from the block of 8 range switching. In the course of operation of a digital filter, a smooth tuning of its frequency characteristics is performed by a control signal applied to a fine frequency tuning input of a quantizing oscillator 1 (filter input 10).

Thus, for signal processing, only two sequences of control pulses from generator 1 to annular signals are required.

shift registers 3. One of them is low-frequency, followed by a quantization frequency. The pulses of this sequence are fed to the control inputs of the recording of the ring shift registers 3 and ensure that the previous value of the output signal from the accumulating adder 7 and the next, value of the input signal from the analog-digital converter 2 is written to registers 3. Another sequence of pulses is a high frequency follow-up frequency multiple to the quantization frequency. The pulses of this sequence arrive at the control inputs of the shift of registers 3 and provide, in turn, during the quantization period, issuing to the block b all the values of the input and output stored in the shift registers 3.

The ability to control the processing of signals using only two sequences of control signals makes it possible to significantly simplify control of the filter and make it possible to control the processing of signals without resorting to using special blocks to distribute addresses in the storage device. This reduces the equipment and increases its reliability. and, accordingly, the reliability of signal processing results.

Claims (2)

1. US Patent No. 3703632, cl. 235-152,1972. 2. For registration No. 2311866 / 18-24, 1976, according to which a positive decision was made on the issuance of copyright testimony. P