SU646331A1

SU646331A1 - Binary number divider

Info

Publication number: SU646331A1
Application number: SU752197684A
Authority: SU
Inventors: Евгений Яковлевич Марголин
Original assignee: Предприятие П/Я А-7284
Priority date: 1975-12-08
Filing date: 1975-12-08
Publication date: 1979-02-05

Description

(54) УСТРОЙСТВО ДЛЯ ДЕЛЕНИЯ ДВОИЧНЫХ ЧИСЕЛ(54) DEVICE FOR FISSION OF BINARY NUMBERS

дешифратора нул , выход которого соединен с первым входом бпока регистрации нуп и единицы, второй вход которого соединен с выходом старшего разр да регистра депитеп , п тый выход бпока управлени соединен со вторым входом эпемента ИЛИ, выход которого соединен со вторым управл ющим входом регистра частного.the zero decoder, the output of which is connected to the first input of the nup registration and the unit, the second input of which is connected to the output of the high bit of the register depot, the fifth output of the control side is connected to the second input of the OR, the output of which is private.

Сущность изобретени заключаетс в предварительном сдвиге делител влево до тех пор, пока в старшем разр де регистра депитеп не будет зйписана единица, запоминани в счетчике количества разр дов, на которое сдвину делитель , и в последующем сдвиге на это Количество разр дов содержимого регистра частного. Врем , необходимое Дпйсдвига делимого и делител , равно произведению удвоенного числа старших нулевых разр дов делител , то есть 2бс К,на врем сдвига одного разр да.The essence of the invention consists in preliminary shifting the divider to the left until the unit stores the unit in the high register register, storing in the counter the number of bits by which the divider is shifted, and in the subsequent shift to this number of bits in the register private. The time required for the division of the dividend and the divider is equal to the product of the doubled number of the leading zero bits of the divider, that is, 2b K, by the time of the shift of one digit.

Известно, 4To2 og2K KnpH К 2, то есть при сдвиге делител получаетс выигрыш во времени по сравнению с вычитанием делител .It is known that 4To2 og2K KnpH K 2, that is, when the divider is shifted, there is a gain in time compared to the subtraction of the divider.

На чертеже представлена структурна схема устройства.The drawing shows a block diagram of the device.

Устройство содержит: первый бпок управлени 1, сумматор 2, регистр делимого 3, регистр делител 4, регистр частного 5, элемент ИЛИ 6, блок 7 регистрации нул и единицы дешифратор нуп 8, реверсивньтй счетчик 9.The device contains: the first control box 1, the adder 2, the register of the dividend 3, the register divider 4, the register of private 5, the element OR 6, the block 7 of the registration zero and the unit decoder nup 8, the reversible counter 9.

Принцип работы устройства закпгочаетс в следующем.The principle of operation of the device is summarized as follows.

До начала операции делени делимое записываетс в регистр 3 делимого, делитель - в регистр 4 делител . Счетчик 9 устанавгатаетс в нуль. Если в старшем разр де регистра 4 делител записан иупь, то на вход цепи сдвига регистра 4 делител с первого сдвигового выхода блока 7 управлени .поступают импульсы, сдвигающие влево содержимое регистра 4 делител до -тех пор,. пока в его старшем разр де не по витс единица, что фиксируетс бпоком 7 управлени по входу регистрации единицы.Prior to the start of the division operation, the dividend is recorded in the register 3 of the dividend, the divisor is recorded in the register 4 divisor. Counter 9 is set to zero. If the higher division of register 4 of the divider is recorded by iup, then pulses are fed to the input of the shift circuit of the register 4 of the divider from the first shift output of the control unit 7. The pulses are shifted to the left by the contents of the register 4 of the divider until-then. as long as its highest bit is not in accordance with the unit, which is fixed by the control side 7 at the unit registration input.

Процесс депени производитс по алгоритму, согласно .которому депимое сравниваетс с далитепем; если оно больше-- то старший разр д частного единиц .о, если меньше - то нупь. В зависимости от исхода сравненв формируетс первый остаток, который рав&й либо рэзности делимого и депите The deposit process is carried out according to an algorithm, according to which the deposit form is compared with the distance given; if it is greater, then the highest bit of private units .o, if less, then nup. Depending on the outcome, a first residue is formed, which is equal to or raznost of the dividend and

(если делимое больше делител ), либо самому делимому (если оно меньше). Далее остаток удваиваетс , сравниваетс с делителем, формируетс втора цифра частного и т. д.(if the dividend is greater than the divisor), or to the dividend itself (if it is smaller). The remainder is then doubled, compared with the divisor, the second digit of the quotient is formed, and so on.

Сравнение детамого со сдвинутым делителем производитс в сумматоре например путем добавлени к лепимому дополнитепьного кода депитеп , который получают обращением разр дов регистра 4 депител (при поступлении управп юш;его сигнапа обращени кода с блоком 1 управлени ) и добавлением единицы на вход переноса младшего раэр да сумматора 2 (единица поступает от бпока 1 управпени по цепи подачи единицы). Результатом сравнени вл ес наличие или отсутствие единицы на выходе переноса старшего разр да сумматора 2, котора фиксируетс блоком 1 управпени ( по входу регистрации единицы переноса). При напичии единицы переноса (делимое больше делител ) разность между делимым и делителем поступает по управл ющему сигналу выдачи суммы .блока 1 управлени в регистр 3 делимого, бпок 1 управпени формирует единицу старшего разр да частного, котора записьшаетс в младший разр д регистра 5 частного по цеп выдачи цифр частного.Comparison of the part with the shifted divider is made in the adder, for example, by adding an additional depot to the modem, which is obtained by inverting the digits of the depot's register 4 (when control is received; its reference code is received with control block 1) and adding a unit to the transfer input of the junior rar and adder 2 (unit comes from 1 control unit supply circuit). The result of the comparison was the presence or absence of a unit at the transfer output of the higher bit of the adder 2, which is detected by the control unit 1 (at the registration input of the unit of transfer). When a transfer unit (divisible more than a divider) is typed, the difference between the dividend and the divider is received by the control signal of issuing the sum of control block 1 to the register 3 of the dividend, the control side 1 forms the high order bit of the private bit, which is written to the low order bit of register 5 private by chain of issuing figures private.

При отсутствии единицы переноса (делимое меньше делител ) само депимое поступает в регистр 3 делимого , в младший разр д регистра 5 частнго записываетс нупь.In the absence of a transfer unit (divisible less than the divisor), the depim itself goes into the register 3 of the dividend, and the lower code is written to the lower order bit of the register 5.

Удвоение первого остатка, записанного в регистре 3 делимого, производитс подачей импульса сдвига по первому сдвиговому выходу блоком 1 управпени . Одновременно импульс сдвига подаетс по второму сдвиговому выходу бпока 1 управпени на цепь сдвига регистра 5 частного. Дапее производитс формирование следующей цифры частного.The doubling of the first remainder, recorded in the register 3 of the dividend, is performed by applying a shift pulse at the first shift output by the control unit 1. At the same time, a shift pulse is applied at the second shift output of the control side 1 to the shift circuit of the register 5 private. Dapee is forming the next private figure.

Claims

After obtaining the required number of quotients of the quotient, pulses are sent from the second shift output of the control unit 7 to the partial shift circuit of the black element 6 OR, and to the subtraction input of the counter 9. When the counter 9 is zeroed, the decoder 8 zero outputs a pulse interruption signal. Thus, the quotient is shifted to the left by the same amount of bits to which the divider was originally shifted. The effectiveness of the invention is to increase the speed. the device is due to the shift of the divider to the left until the divider is written by one in the highest order of the de register. The reduction in the time for obtaining a private in comparison with a known device is due to the fact that when receiving the first digit of a private in a known device, the depositor must be deducted from the dividend to obtain a negative balance. The subtraction time is directly proportional to the magnitude of the excess of the time divisible over the divider, and the time required for shifting the delay is in logarithmic dependence on the magnitude exceeded. This shows that the time required for the shift will be less than the time to subtract the divider from the dividend in the known device. Apparatus of the Invention A device for dividing binary numbers containing a divisor register, a divider register, a private register, an adder, a control unit, the first output of which is connected to the control input of a divisible register, informational input of which is connected to the output of the adder, the output of the divisible register is connected to the first informational input of the adder The second information input of which is connected to the output of the register of the divider, the control input of the adder is connected to the second output of the control unit, the third output of which is connected to the first The second control input of the divider register, the transfer output of the senior bit of the adder is connected to the input of the control unit, the fourth output of which is connected to the first control input of the private register, characterized in that, in order to control the speed, an element, OR, decoder zero, reversible is entered into the device. the counter, the registration unit zero and one, the first output of which is connected to the second input of the register divider and summed up with the input of the reversible counter, the second output of the registration unit zero and the control unit It is connected with the first input of the OR element and the subtracting input of the reversible counter, the third output of the registration unit zero and one is connected to the installation input of the peiwpsive counter, the outputs of which are connected to the inputs of the zero decoder, the output of which is connected to the first input of the registration unit zero and one, the second input of which is connected with the high-order output of the divider register, the fifth output of the control unit is connected to the second input of the OR circuit, the output of which is connected to the second control input of the private register. Sources of information taken into account in the examination 1. The author's certificate of the USSR № 4224147, CP. G 06 F 7/52, 1974,

2.Kartsev; M.A. Arithmetic of digital machines, ed. Science, 1969, p. 492.