SU632108A1 - Clock pulse shaper - Google Patents

Description

The invention relates to computer systems with redundancy and can be applied in redundant pulse clock generators and frequency dividers.

I, 2 clock pulse drivers are known, comprising n oscillators and a switching circuit, output stages and a redundant frequency divider forming the n common-mode pulse signal sequences. .

Their disadvantage is the violation of the in-phase formation of pulse sequences at the time of the generator failure and switching to the backup generator.

The closest technical solution to the invention is a redundant clock pulse generator 3 containing a master oscillator, a frequency divider, an AND element, a trigger, and a majority element in each channel.

However, during the failure of a working generator or a multi-stable trigger, pulse outputs may occur at all outputs of the driver, the duration of which is random.

The aim of the invention is to improve the reliability of the device, in particular, by providing deterministic pulse signals on most outputs, the pulse duration and period of which are located in deterministic time intervals at the time of the occurrence of a single fault in the channel or trunk stages.

The goal is achieved by the fact that in the proposed device each channel

contains a delay element and a single pulse shaper, the inputs of which are respectively connected to the master oscillator and the output of the majority element, and the output is connected to the installation inputs in “About the frequency divider and through the delay element to the installation input in“ About the trigger. The installation input into “1” is connected to the output of the element I, and the output of the trigger of each channel to the corresponding inputs of the majority element of each channel.

The drawing shows a block diagram

redundant clock pulse.

The clock pulse shaper contains in each channel the master oscillator 1 connected to frequency divider 2 and delay element 3. The outputs of the divider are connected to element 4, the output of which is connected to the input setting 1 trigger 5. The output of the majority element b is connected to the driver 7 of a single pulse, and the inputs - with the outputs of 8-10 corresponding triggers.

The device works as follows.

When the power is turned on, the generators are excited 1. Since the generators are randomly excited, first in one NC channels, for example in the first one, the corresponding combination of signals on AND 4 element is recruited, which translates trigger 5 into a single state. Then, for example, in the second channel, the trigger 5 is also transferred to a single state. Majority element 6 is triggered in all channels, and as a result, in each channel, if there are signals from a 1 fs generator, a single pulse is generated using a shaper 7. Using single pulses, the operation of frequency dividers of different channels is synchronized with an accuracy of the period of the generator signals.

For a stable formation of a single pulse and the phasing of clock pulses of various channels, the zeroing of the triggers 5 must be carried out with a delay determined by the following expression

 + At + Ato,

where T is the duration of the period of the signal generators 1,

D1 is the spread of the signal delays introduced by the highway connecting trigger 5 with elements 6;

And to-scatter the delays of the signals introduced by the driver of a single pulse.

Thus, providing output signals with specific time intervals at the time of the occurrence of a single fault in the cascades to the trunk of any channel is achieved by generating output signals (for example, signals taken from the splitter 2) on each channel independently; through the majority element, which is insensitive to a single fault. This ensures high reliability of the device and allows repairing any of the failed channels.

Claims (3)

1. Author's certificate of the USSR No. 427480, M. KL.2 N 03 K 23/00, 1971. 2. USSR author's certificate № 477545, M. Kl. H 03 K 23/00, 1972. 3. USSR author's certificate 0 No. 488209, M. Kl.2 G 06 F P / OO, 1973. n-ntffn