SU1617647A2 - Device for correcting time scale - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to expand the functionality. The time scale correction device contains grs 1 clock pulses, dividers 2 and 3 frequencies, register 4, electros AND 5 and 11, comparison block 6, triggers 7 and 8, driver 9 pulses, RS-trigger 10 and electro OR 12. The goal is achieved by providing a two-way correction, which results in a time scale shift of 0.4 s in both the lagging and the leading direction. The device of clause 2 of the file is distinguished by performing a splitter 2 frequency. 1 hp f-ly, 8 ill.

Description

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Phys. 1

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The invention relates to radio engineering and can be used in measuring systems.

The aim of the invention is to enhance the functionality by providing a dyesthetic correction.

FIG. 1 shows a block diagram of a time scale correction device; in fig. 2 is a frequency divider block diagram: in FIG. 3 — timing diagrams, but noting the work of the first frequency divider; in fig. 4–8 are time diagrams showing the operation of the proposed device.

 The time scale correction device has a clock clock pulse generator I,: the first and second dividers are 2 and 3 frequencies,: register 4, elemiFiT 5, block 6 comparison,

flip-flops 7 and 8, pulse shaper 9, RS-flip-flop 10, additional element AND 11 and element OR 12, with the first frequency divider 2 containing frequency divider 13, flip-flop 14, first and second elements 15 and 16.; The device for correcting the time scale is; bots as follows. ; Generator 1 is a source of pulses with a period T, for example, μs (Fig. 4, c), to start divider 2, which; has a division factor of K, for example. In divider 2, the pulses of generator 1 are fed to the counting input of divider 13, which has a division factor K / 2. : Ia output of the highest bit of the divider - 13: (| pulses with a frequency of 2 Hz Lfig. 3, e), which arrive at the counting

| trigger input 14 and the first inputs of the elements 15 and 16. Trigger 14 divides the frequency of pulses arriving at its counting input by 2. Phase pulses with a frequency of 1 Hz from the direct and inverse outputs of trigger 14 (Fig. 3, 6. s) arrive at the second inputs of the elements 15 and 16, respectively, and are gated with pulses

2 Hz (Fig. 3, a). At the outputs of the elements And 15

and 16, i.e. at the main and additional outputs of the divider 2, pulses are generated with a frequency of 1 Hz, i.e. second pulses (Fig. 3, g, g and Fig. 4, g, d), with the pulses at the additional output being shifted relative to the impulses at the main output by half of their repetition period, i.e., 0.5 s.

From the main output of the divider, the 2 second pulses through the element 12 arrive at the input of the divider 3 (Fig. 4, g), which absorbs the time (seconds, minutes, hours), the signals generated by the dividers 2 and 3 form a time scale.

The second pulses from the main and auxiliary outputs of the divider 2 (Fig. 4, dd) arrive respectively at the installation inputs in "O (R) and" b (S) RS-flip-flop a), the output of which generates a signal in the form “I, corresponding to the second n () of the period of repetition of second pulses at the main output of divider 2 (FIG. 4, k). This sig

five

five

five

Yu

0 n

It arrives at element 11, permitting only Bd signals to pass through it, the time of the second half of the repetition period of the second impulses.

In the initial state at the inverse output of the trigger 8 there is "b" (Fig. 4.6), which is connected to the input of the installation in the trigger 7, prohibiting its change under the influence of signals at the counting input. "About the output of the trigger 7 (Fig. 4, g) prohibits the passage of signals through the element And 5. La output of the imaging device 9 is present" O (Fig. 4, ").

If there is a difference in the temporal position of the second pulses at the main output of the divider 2 and the second pulses of the reference clock, the correction is made. Not a correction code in register 4 is specified. A correction code is written, which is defined as follows.

If the second pulses at the main output of the divider 2 are ahead of the corresponding second pulses of the reference clock, then the code is determined by the absolute value of the difference in DT between the corresponding second pulses. If the second pulses at the main output of the divider 2 are lagging behind the corresponding second ones-. pz of the reference clock, the code is determined by the value that complements the AT divergence to a full second.

Thus, the correction code is equal to:

N

AT | at

WITH

 KT-1DT1 with -, (1)

where t

I;

pulse repetition period

nerator 1;

the division factor of divider 2. After the code is written into register 4, a "pulse input" is applied to the correction input (Fig. 4, a), which sets the trigger 8 to one state. "About the inverse output of the trigger 8 (Fig. 4.6) is fed to the installation R input of the trigger 7, allowing its state to change under the influence of signals on the counting input.

The binary code from the outputs of the bits of the splitter 2 is fed to the first inputs of comparison unit 6, the second inputs of which receive the correction code from the outputs of register bits 4. When the codes of the output of block 6 coincide, a pulse is formed (Fig. 4, "), which is ahead of the next second pulse on the main output of divider 2 by

A. (K-N) T. (2)

The first impulse (Fig. 4, e) from the output of block 6 (after the impulse was applied to the machine bar, “Correction input) reverses trigger 7,“ I from whose output (fig 4.m;) permits the projection of signals through AND 5 The next impulse from the output of block 6 passes through an AND 5 element (Fig. 4, L) and simultaneously flips up the trigger 7 with a slice (Fig. 4, g). A pulse from the output of the element 5 starts the shaper 9, at the output of which a pulse of a certain duration is formed (Fig. 4, s). This pulse is applied to the control input of divider 2 and resets it. At the same time, this pulse arrives at the counting input of the trigger 8, which returns to the initial state. "1 with the inverse output of the trigger 8 (Fig. 4.6) is fed to the installation input of the trigger 7, prohibiting the change of its state under the influence of signals on the counting input.

Thus, as a result of the reset, the divider 2 starts counting the pulses of the generator 1 from zero to the time A earlier. - The impulse from the output of the imaging unit 9 (Fig. 4, s) also goes to the second input of the AND II element, to the first input of which a strobe signal is output from the output of the trigger 10 (Fig. 4, ":). corresponding to the second half of the repetition period of second pulses. If the pulse at the output of the imaging unit 9 appears in the first half of the period of one-second pulses, which corresponds to a positive divergence, then the impulse from the output of the imaging unit 9 does not pass through element 11. If the impulse from the output of the imaging generator 9 appears in the second half of the period of second impulses ( Fig. 4, i), which corresponds to a negative divergence, the pulse from the output of the imaging unit 9 passes through the element 11 and 11 (Fig. 4, l), opened by a signal from the output of the RS flip-flop 10 (Fig. 4, k); and through the element OR 12 enters the input of the divider 3 (Fig. 4, g), the compensator is missing a 2-second pulse as a result of resetting the divider. This correction ends.

Thus, the proposed device provides a two-way correction, i.e. in the direction of lagging and in the direction of advancing.

Example. Let the second pulses at the main output of the divider (Fig. 5, a) be ahead of the corresponding second pulses of the reference clock (Fig. 5.6) by 0.4 s, i.e. discrepancy, 4 s. In accordance with formula (1), the correction value N must correspond to this discrepancy, and the divider 2 is reset 0.4 seconds after the i-ro second pulse is generated at the main output (Fig. 5a) at the time of the i-ro second pulse formation reference hours (Fig. 5.6). Since the pulse at the output of the imaging unit 9 appears in the first half of the period of the second impulses, when the RS flip-flop 10 is in the zero state, it does not pass through the element AND P. After the correction, the corresponding second impulses of the proposed device and the reference clock coincide. Thus, as a result of the described correction, the time scale is shifted by 0.4 s to

side lag.

The iiycTb second pulses at the main output of the divider 2 (Fig. 6, a) lag behind the corresponding second seconds of the reference clock (Fig. 6.6) by 0.4 s, i.e. LT difference: -0.4 s. In accordance with formula (1), the correction value N must correspond to the value that complements the LT difference (absolute value) to the center of seconds. In this case, the splitter 2 is reset after 0.6 s after the i-ro second pulse is generated at its main output (Fig. 6, a) at the time of the i- | -l-ro second pulse of the reference clock (Fig. 6.6 ). Next i + 1st

A 5 second pulse at the output of divider 2 appears at the time of the formation of the i + 2 second pulse of the reference clock. To ensure that this situation does not lead to an error in the formation of the time scale in 1 second,

0 that takes place in the prototype, the proposed device provides the following. Since the pulse at the output of the imaging unit 9 is formed during the second half of the period of one-second pulses at the main output of the splitter 2, when the RS flip-flop 10

5 is in the single state, then the pulse from the output of the imaging unit 9 through the elements AND 1 1 and OR 12 passes to the input of divide. 3 (Fig. 6, a), to compensate for the missing jl-1 second pulse at the output of the divider 2. The next 1 - (- 2nd second impulse arriving at the input of dash line 3 from the output of divider 2 coincides with the i + 2 nd second pulse of the reference clock. Thus, as a result of the described correction, the time scale is shifted by 0, 4 with "in advance.

The correction range in the proposed device is (-0.5 s, +0.5 s) with and and T 1 ISS. If the discrepancy exceeds ± Ct5 s, then the combination of the corresponding second impulses of the device and the reference clock can be carried out by a double correction by

0

N

fKT-AL / with f;

yt

Yt

f at

For example, if the second impetus at the output of divider 2 (Fig. 7, a) lags behind the second impulses of the reference clock by 0.6 s, i.e. , 6c, then it is necessary to carry out a correction twice by the value - | DT | / 2 0.7 s.

After. the first correction is the discrepancy, 3 s, and after the second (Fig. 7.a, b).

If, 6 s (Fig. 8, ag. B), then it is necessary to carry out a correction twice by a value of 3 s.

After the first correction, 3 s, and after the second (Fig. 8, a, 6}.

FIG. 6.6, and 8.6 signals correspond to the signals at the output of the element OR 12 (Fig. 1, l).

Claims (2)

1. The device for correcting the time scale according to the author. St. No. 1363509, characterized in that, in order to expand the functionality by providing two-sided correction, serially connected RS flip-flop, an additional AND element and an OR element are introduced, the first and second frequency dividers are connected in series through the OR element, the output of the first frequency divider is connected to the installation input in the “About RvS trigger”, to the installation input in “1 of which the auxiliary output of the first frequency divider is connected, and another input of the additional element And the output of the pulse former is connected. 2. A device according to claim 1, characterized in that the first frequency divider is designed as a frequency divider, the output of the higher bit which is connected to the counting input of the trigger and the first inputs of the first and second elements And, the second inputs of which are connected respectively to the direct and inverse outputs of the trigger, and the counting input 0, the frequency divider is the counting input of the first frequency divider, the control input of which is the setup input of the frequency divider connected to the setup input of the trigger, the outputs of the first and second I elements are respectively the output and additional output of the first frequency divider, the other outputs of which are the outputs of the bits of the frequency divider and the direct output of the trigger. (riaz  iA t K12 I / (- 1K 1 J M-1N X-l K 1 JJtf-J / lfJV f K1  PPP, .PPP.PPP.PP.PPP., PPP.PPPPPPPP., PPP..PPP Ts3ig.1 Schi 5 / Correction 1 correction FIG. Reset Reset Korrektsi 1Korreshchi 2 Shig.d