SU624227A1 - Arrangement for raising binary number to power - Google Patents

Description

Ie-regression relates to computing technology and can be applied when constructing special computing devices and functional information converters.

It is known a device for raising a binary number to the fourth degree, containing the elements of a zarezhka, a binary counter, the outputs of which through the first | gruppa of elements I are connected to the input of the first adder, whose outputs through the second and third groups of elements And are connected to the inputs of the second adder, the outputs of which through the fourth a group of elements And connected to the inputs of the third adder. It has a low response rate, since the initial number is represented in the vice special mode, the pulses, for treating each of which the device is spent four times. The closest technical solution to the invention is a device for raising a binary number to a power, containing g / - digit register of a number and three summations

ra, and the output of each digit register of the number is connected to the input (+1) of the first adder, the device shift bus is connected to the shift register inputs of the number, the first and third adders, the first information input of the device is connected to the input of the lower digit register number. This known device is characterized by a large amount of equipment and KIM speed, caused by the sequential nature of information transmission through a long chain of series-connected blocks.

The purpose of the invention is to reduce the amount of equipment and increase speed. In the proposed device, this is achieved by the fact that the output of the first adder is connected to the inputs of the first and (+1) th bits of the second adder, the output of the ith discharge is connected to the input (+ 1) th bit of the third adder, the forward output of the th digit register of the number is connected to the input of the 4th digit of the second adder, the inverse output of the I-th serial register of the number is connected with the input (i +1) - of the third discharge, second information input of the device mpatsshego jiaapaaa to the input of the first adder and the third - with vhotsom mpatsshego raar tsa and older with vhotsom starting with (H b2) -th, raar ATC third adder. In the drawing, the schematic diagram of the device of a central processing unit of the total number of degrees is shown. It combines tf — a rasor register of 1 chip, adders 2, 3, and 4, the first, second, and third information points of the 5, 6, and 7 devices and the bus 8 of the scroll. The initial state of register 1 and the Matorov 2 sum, 3 and 4 is zero. With the arrival of a pulse on bus 8, the contents of register 1 and adders 2, 3 and 4, respectively, are set to otsin, tsva, three and four pieces left, then an information pulse 5, 6 and 7 arrives on the edge of the postcameral calf, which is implemented: in the second cycle - adding to the contents of the third adder 4 the second sum of the matrix 3 and the first adder 2 of the equalized (with a shift to the occ bit to the left) core of the second 3, first 2 adders and the register 1, adding to the contents of the second adder 3i tre the second adder 4, respectively, of the forward and backward inverted register register Ij and the addition of digits; in the smallest bit of the first adder 2 on the entry point b, with the addition of the second and the lowest ones, starting with (rt +2) -th, the bit of the third adder 4; in the third cycle - addition to the contents of the second adder 3 of the ends of the first adder 2 and adding the value to the register 1 to 5; in the fourth cycle, the fourth adder of a military unit (with a shift to the occ bit to the left) of the second adder 3 is added to the content of the third adder. After four p-ts, hert f is the number of the final special-end number, in the first 2, in, The third and the third 4 accumulators accumulate the current code value, respectively, of the square of the cube and the fourth power of the consecutive number of the numbers received on the information pages 5, 6, and 7. The operation of the preprinted device is illustrated in the table.

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Claims (1)

11 The proposed device, in comparison with the known one, has a smaller amount of equipment due to the elimination of part of the blocks and a large speed action due to the reduction in the number of cycles spent on processing each digit of the number, since in the known device and the fourth degree, nine cycles are spent, and in the proposed - four cycles, i.e. The speed of 1shint is 2.25 times. Apparatus of the Invention A device for raising a binary number to a power containing a bit register of a number and three adders, with the output of each jth digit of the number register connected to the input of the (+1) th digit of the first adder, the shear bus, devices connected with reO1OO shift inputs OOO10OOO ОО1ООО 01O1 OQ1O10 00010000-4 2 Y lH11011-4 (2X + i) OOlOOl 00110110 OOlOOl OllOll OlOlOOOl the number of the first and the third sum of the tori, the first information input is connected to the input of the junior & number register, characterized in that, in order to reduce the equipment and speed up, the output is The first bit of the first mat is connected to the inputs of the i th and (1 +) th bits of the second adder, the output of the i - th bit of which is connected to the input of the (i +1) th regr and the third adder, direct output - the first of the number register is connected to the input of the second digit of the second adder, the inverse output of the i -th p On the other hand, the chirp register is connected to the input (+1) of the third adder of the third adder, the second information input of the device is connected to the input of the lower order of the first adder, and the third to the input of the younger order and with the inputs of the older one, starting from (c +2 ) th, third adder. l4 // K / d