SU612236A1 - Information input arrangement - Google Patents

Description

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The invention relates to computing and can be used in the input blocks of computing devices.

Signal reception devices are known, comprising a clock pulse generator, a filter, a multiplier, a subtractor, an interrupter, an analysis unit and a series-connected stable pulse generator, a yipulse period pulse converter, a correlation pulse period converter to the frequency detuning code, a voltage code converter | Tj

The disadvantage of the known devices is their complexity.

The closest technical SU1F1OST to the proposed one is a signal sampling device containing AND elements, NOT elements and a pulse generator, the output of the generator pulse is connected to the first inlet of the first element And the second input. which is connected to the output of the first element is NOT, the output of the second element is NOT connected to the first input of the second element AND C2j.

The disadvantage of this is that the device consists in the low reliability of data entry with large delays.

signals, i.e. signals delayed by the communication line for more than a period of impulse impedance.

The purpose of the invention is to increase the reliability of the input.

Claims (2)

The goal is achieved by introducing two triggers, a delay element and a shift register connected by the output to the information output of the device, and the input to the information input of the device, the second input, the NOT element, and through the delay element - the first The output of which is connected to the input of the first element NOT and the auxiliary input of the first trigger, the second input of the element AND is connected to zero at the output of the first trigger, the single input of which is connected to the output of the first element And connected to This input with sec is the third element with a single output of the second trigger, the single and zero BKOf of which are connected respectively to the input of the device installation and the output of the second element I, controlling the input of the shift register connected to the output of the fourth element I, the first input of which is connected to the zero output of the second trigger , and the second input - with the output of the pulse generator and the clock output of the device. FIG. 1 shows a block diagram of the proposed device; in fig. 2 - time diagram of his work. The device contains a generator of 1 pulses, triggers 2 and 3, the elements And 4-7, the elements NOT 8 and 9, the delay element 10 and shift registers 11. The device operates as follows. When the device is turned on, the trigger with the initial setup signal OO is set to the state. From the pulse generator 1, information request signals are output to the communication channel. The same signals through the And 7 element set the trigger 3 to the state. In response to the request signals, information is received via the communication channel, the first two times the Kotapon row is always O. The signal passes through the delay element 10 R And 6, closes the passage - through the element And 7 pulses into the state O. The signal O from the info {4-channel channel through the element NOT 8 enters the input of the open element AND 5 and sets the trigger 2 8 to the zero state. In this case, element 4 also opens and allows the arrival of shift signals from oscillator 1 to the control register shift register 11. Next, information from the communication channel arriving at shift register 11, advances toward hundred (100 bits. Use Devices allow receiving reliable information into computers irrespective of the amount of delay created by the cable entry. Formula of the Invention A device for entering information containing AND elements, NOT elements and a pulse generator, the output of the generator of pulses Connected to the first input of the first element AND, the second input of which is connected to the output of the first element NOT, the output of the second element is NOT connected to the first input of the second element AND, different in that JTO, in order to increase the reliability of the input, two triggers, a delay element and the shift register connected by the output to the information output of the device, and the input to the information input of the device, the input of the second element NOT and through the element of the delay to the first input of the third element I, the output of which is connected to the input of the first element NB and zero input of the first trigger, the second input of the second element I is connected to the zero output of the first trigger, the single input of which is connected to the output of the first element I, connected by the third input with the second input of the third element I and e shichnm output of the second trigger, single and zero the inputs of which are connected respectively to the input of the device installation and the output of the second element I, the control of the shift register input is connected to the output of the fourth element I, the first input of which is connected to the zero output of the second th flip-flop and the second input - to the output pulse generator and timing-output unit. ... Sources of information taken into account in the examination: 1. Copyright certificate (SICR 457182, M. class. 06 G 3/02, 197: 2. 2. Patent of Great Britain 1423689, M.cl. H 03 K 5/00, 1975. - nJ LrLJTJlJlJlJlJTJTJl-4 ibnjlJTJbnJl riJlJ-LJljn m jiJTjijijanjijiJiJijTrLn