SU610115A1 - Differentiating-smoothing device - Google Patents

Description

one

This invention relates to the field of computing technology and is intended for use in devices and control systems for various objects.

A device for differentiating 1 is known, comprising a reference frequency generator, five counters, a divider, a result counter, a trigger, four groups of prohibition circuits (And elements) and one prohibition scheme (And element). This device is designed to calculate the derivative of the reciprocal of the input code. By adding one additional result counter and repeating the conversion cycle, the device can be used to differentiate the input signal.

However, the functionality of the device is limited because it does not allow the calculation of the second derivative. The low quicker operation of the device is caused by the need to double the code into a time interval (for each sample of the input sequence), and the lower accuracy is due to the fact that differentiation is performed without smoothing out random errors.

A digital smoothing device 2 is known, which contains two accumulating adders of bits each (pit input information width and constant multipliers, respectively) and an n-bit register.

The disadvantages of this device are: limited functionality, since it is intended only to smooth out random noise in the input signal and does not calculate the first and second derivatives of the input signal, and the low accuracy of the calculation, due to lack of compensation for the first and second derivatives Signals whose useful component is described by a polynomial of the first and second degrees as a function of time.

Of the known devices, the most blunt to the technical essence of the invention is the differentiating-smoothing device | 3J, designed to calculate the smoothed values of the first derivative of the measured signal with the applied a. Additive uncorrelated random noise.

This device contains a memory unit, a Fourier – Rademacher spectral coefficient calculation unit, a shift register, an adder, and a control unit. The device input is connected to the first information input of the operational memory block, the output of which is connected to the first input of the block

calculating the spectral Fourier Rademacher coefficient, the first output of which is connected to the first input of the main register. The output of the shift register of the subfc is unified to the first input of the adder, the output of which is connected to the first output of the device, the outputs of the control unit from the first to the fifth are connected respectively to the second inputs of the adder, the shift register and to the second, third and fourth inputs of the calculator of the spectral Fourier – Rademacher coefficients .

However, with the help of this device, it is possible to determine the smoothed value of the first derivative of the input signal without dynamic error only for the case when the useful component is described by a polynomial of the first degree. The device is not intended to calculate the current smoothed values of the input signal and its second derivative.

In addition, in the device, each duty cycle for calculating the derivative is preceded by the step of updating the input signal sample. resulting in a sequential shift of information B to a single memory unit of the RAM, which leads to 2 N-fold execution of operations for the OM (N is the volume of the input sample, the volume of the RAM) and a decrease in the speed of the device.

In such a device, the accuracy of calculations is reduced due to the absence of compensation for the second derivative of the signal, the useful component of which is described by a polynomial of the second degree.

The aim of the invention is to expand the functional capabilities of the device, improving speed and accuracy of its operation.

The goal is achieved by the fact that modulo two summation, address generation, switching, two comparison circuits are introduced into the proposed differentiating-smoothing device. The outputs of the control unit from the sixth to the tenth are connected respectively to the five inputs of the address generation unit, two outputs of which are connected respectively to two control inputs of the RAM, the second information input of which is connected to the output of the adder, and the output to the second output of the device. The eleventh output of the control unit is connected to the fifth input of the Fourier-Rademacher spectral coefficients calculation unit, the second output of which is modulo-two summed connected to the first input of the switching unit, the forward and inverse outputs of which are connected to the sixth and seventh calculations of the calculating unit Fourier - Rademacher spectral coefficients. The second input of the switching unit is connected to the twelfth output of the control unit, three inputs of which are connected respectively to the outputs of two comparison circuits and the third output of the calculation unit of the Fourier – Rademacher spectral coefficients whose first output is connected to the inputs of two comparison circuits.

In addition, in the device, the modulo-two summation unit contains (n - 1) groups

modulo-two adders, with the first (the modulo-two inputs of each group are combined and connected respectively to one of the first (n - 1) bits of the n-bit input of the block. The second inputs of the modulo adders are two of each group are connected respectively to one of The bits of the p-bit of the block's input, starting with the bit whose number is one greater than the group number. The output of each modulo-two adder is connected to one of the m bits of the output of the block.

The switching unit of the device contains m elements AND, elements OR, NOT. The first inputs of the And elements are connected to m bits of the first input of the switching unit. The second inputs of the AND elements are connected to m bits of the second input of the block, the output of each element and connected to the corresponding input of the OR element, the output of which is connected respectively to the direct output of the block and the input of the element NOT whose output is connected to the inverse output of the block.

The block of formation of addresses in the device contains a counter, a reversible counter, a decoder and a trigger. The counting input of the counter, the counting and control inputs of the reversible counter, the single and zero inputs of the trigger are connected respectively to the five inputs of the block. The outputs of the counter and reversible counter are connected respectively to the first and second inputs of the decoder. A single trigger output and a decoder output are connected respectively to the first and second outputs of the address generation unit.

The Fourier – Rademacher spectral coefficients calculation block contains an adder-subtractor, a Rademacher function generator, a switchboard, AND elements, OR elements, one of which is connected between the forward switch output and the first input, the first AND element, and the OR the first input of the second element I. The second inputs of the elements And connected to the third input of the block, the outputs are connected respectively to the first and second inputs of the adder-subtractor, the third and fourth inputs of which are connected to respectively to the first and fifth inputs of the block, the first and second outputs respectively to the first and third outputs of the block. The fourth input of the block is connected to the input of the Rademacher function generator, the output of which is connected to the second output of the block and the first input of the switch, the second input of the switch is connected to the second input of the block, the sixth and seventh inputs of which are connected respectively to the second inputs of the first and second OR elements.

FIG. Figure 1 shows a block diagram of a differentiating-smoothing device containing an operative memory unit 1, a unit 2 for calculating Fourier-Rademacher spectral coefficients, a shift register 3, an adder 4i and a control unit 5. The device input 6 is connected to the first information input of the RAM unit 1, the first output 7 is connected to the output of the adder 4. In addition, the device contains a block 8 of modulo two. block 9 of formation of alros, block 10 of switching, circuits 1, 12 comparison. the second output 13 of the device connected to the output of the memory block I. At tp 2 there is a block 8 modulo summation block diagram containing (n - 1) modulo two adder groups, n-bit input 14 and t-bit output 15. In FIG. 3 is a diagram of an address generation unit 9 which includes a counter 16, a reversible counter 17, a decoder 18, and a trigger 19. Five inputs 20-24 of the block are connected respectively to the counting input of the counter 16, to the counter and control inputs of the counter 17, to a single and zero inputs of the trigger 19, two outputs 25 and 26, respectively, to a single output of the trigger 19 and the output of the decoder 18. FIG. Figure 4 shows the block 2 of the calculation of the Fourier-Rademacher spectral coefficients, containing the adder-subtractor 27, the generator 28 of the Rademacher functions, the switch 29, the elements And 30 and 31, the elements OR 32 and 33 and the first input 34, the n-bit second input 35, the third 36, the fourth 37, the fifth 38, the sixth 39 and the seventh 40 inputs and the first 41, the second 42 and the third 43 highways. The device implements a second-order digital differentiation-smoothing filter algorithm in the spectral domain of the binary orthonormal space of WALSHAG () Co (j) (1) g. And - n-t. tJJ4- /, l j4 «f.w О 2 (N-l) where fo (j). JTiCj). ifsCj) - output parameters of digital filters of the corresponding zero, first and second order for the cases of approximation of the input signal, respectively, fully zero, first n and second degrees; o (j), Cr (). .2 (j) are the spectral coefficients of the zero, first, and second ranks of the input unsmoothed string, respectively; x (j - I) j is the current discrete time; N 2 - the dimension of the input sample (n 1, 2 ...); At is the sampling interval; I - variable dnskretna (O, 1, 2, ..., N - 1). The device allows the calculation of the smoothed values of the signal and its two transceivers. For the dynamic error in the smoothed values of the input signal and its first derivative, the calculation of the smoothed parameters (1troits according to the compensation scheme. The device is adapted to the input signal by analyzing the threshold values of the corresponding spectral coefficients, this property has a pattern Walt, which consists in the fact that the second-order polynomial signal decomposition polynomial signal does not contain rank coefficients greater than two. Maintenance work differenniruyuyhe-straighteners in this case pri.met GNI ... 1G h 0) np '/ C. pr “/ ,, i (,) (H-OAt r, (j) P f fi (P. (5) IP for NjlMi (p (Nzl) Md) Mir (i), (J) y. (j) where X (J), X (j), X (j) - respectively, the current value of the smoothed values of the input signal and its first and second derivatives P 1 and P2 - respectively noporoBbie of the magnitude of the spectral coefficients С | н efj Values of the input non-smoothed signal) t (j - i), required constant calculations of the constant, and the resulting parameters are stored in block I of the operational memory, which for this purpose is divided into two zones, one of which serves to store the N-dimensional input sample, and the second are intended for omini working constants n the calculation results. Working coistitis is entered into memory block I in advance before the main operation of the device. The cell addresses of both zones are generated using address address block 9, and the zone sign is formed on trigger 19. The addresses of the memory zones of the memory These allotted for working counts and results are formed on the counter 16, and the addresses of the cells of the input sample area - using the counter 17. Depending on the operation mode of the device, the addresses of the points of the input sample are formed in a way. At the stage of the accumulated input sample, the addresses are formed on the counter 17 in the natural sequence from O to N - 1 by summing on it the number of pulses coming from the control unit 5. In the settled mode, when the sample has already been accumulated, the addresses of the N samples of the input filter, necessary for calculating the spectral Walsh coefficients, are formed in reverse order by subtracting from the content counter 17 the sequence of control pulses from the control unit 5. Since N 2, after N clocks expire, counter 17 returns to the initial state, which determines the starting point number of the sample. The forwarding of the input sample cells when it is shifted along the current time axis by one step is performed by increasing the content counter 17 by the unit. The Fourier-Rademacher spectral coefficients calculation block 2 together with the block 8 modulo two are designed

for calculating the spectral Walsh coefficients of the zero, first, and BTopoio ranks, the value of the Walsh functions of the first rank (Rademacher functions) is generated using the generator 28 Rademacher functions, and the value of the Walsh functions of the second rank using block 8 modulo two.

Differentiating-smoothing device operates as follows.

The control unit 5 generates a setup signal which zeroes the contents of the generator 28, the adder-subtractor 27, the shift register 3, the adder 4 and the counters 16 and the null nullings in the drawings are not shown). Upon completion of the initial settings, the device switches to the accumulation mode of the input sample. In this mode, the signal from control unit 5 triggers 19 is set to one state and the current coordinates of the input signal input to the device 6 are entered into the cells of the first memory block I, whose addresses are generated in the counter 17 of the address forming unit 9. This sequence of actions is repeated N times, after which the device switches to the setting mode.

At the beginning of each set-up cycle (with the exception of the first), the signal from control block 5, which arrives at the counting input of the counter 17 of the address formation block 9, sets in the counter the address of the starting point of the shifted sample. At this address, the current value of the input signal arriving at its first input is recorded in block 1 of the RAM. In this case, a new sample is formed (this operation is not performed in the first cycle, since the sample for the first cycle is prepared at the sample accumulation stage). After that, the device proceeds to the calculation of the spectral coefficients. At this stage, the control unit 5 outputs control signals to the second input of the switching unit 10 and with its help connects the first output (output of the Walsh function of the second rank Wj) of the module 8 modulo-two summing through the OR elements 32 and 33 to the first inputs of the AND elements 30 and 31. Then the control unit 5 begins to synchronously send control signals to the counting input of the counter 17, previously set in subtraction mode, to the input of the generator 28 and to the second inputs of the And elements 31, 30. At the same time, the output signal of the trigger 19 and the contents of the counter 17 h The decoder 18 receives the first and second control inputs of the main memory unit I as a cell address.

The information from the RAM block 1 is fed to the third input of the subtractor 27. If the value of the Walsh function "-JJ (which corresponds to the logical unit at the inverse output of the switching unit 10), then the control pulse passes through the open element 31 to the second input of the adder- you. the reader 27 and the incoming information is summed up with the contents of the subtractor 27. If the value of the Thickness-I function is open, AND 30 is opened and a subtraction operation is performed on the adder 27. After N cycles on the adder-subtractor 27, the spectral coefficient Сз, ко is formed. the second is fed to the inputs of the comparison circuits 11

and 12. In the event that a logical unit is formed at the output of the comparison circuit 12 (i.e., the spectral coefficient value (Gz is greater than the P2 threshold), the device continues to calculate the second derivative in accordance with

by equation (3). At the same time, the contents of adder-subtractor 27 are transferred to the shift register 3, the adder-subtractor 27 itself is nullified, and the signal from control unit 5 is connected to inputs of And 30 and 31 elements using switching unit 10, the next bit of t-discharge output modulo two summation unit 8 (output of the next Walsh function of the second paraig). At the subtractor 27, the next spectral coefficient of the second rank Cs is generated. Parallel to this, the shift register 3 receives the value of C3, which is summed with the contents of the adder 4. Subsequently, the next spectral coefficient is formed on the adder-subtractor 27, and the sum is accumulated on the shift register 3 and the adder 4

5 shifted by the corresponding number of bits (formula (3)) of the transformant of the second rank. Upon completion of the calculation in accordance with formula (3), a binary code of a number with an accuracy of a constant coefficient (which can

be taken into account by scaling) equal to the smoothed value of the second derivative of the input signal. After the calculation of the second derivative is completed, the control unit 5 outputs a signal to the zero input of the trigger

5 and sets it to the zero state, thereby activating the memory zone, which is assigned for storing the final results. The contents of the adder 4 is recorded in the cell of the RAM 1 with the address formed from the zero state of the trigger 19

0 and zero counter contents 16.

If a logical zero appears at the output of comparison circuit 12 (i.e., the second derivative is zero), the device immediately goes to the procedure of writing the zero content of adder 4 to the operational memory unit 1. After recording the result, the adder 4, the shift register 3 and adder-subtractor 27 are zeroed, one is entered into trigger 19, and the device proceeds to the calculation of the first derivative. In this case, the control unit 5 issues

0 signals to the second input of the switch 29 and with its help through the elements OR 32 and 33 connects the outputs of the corresponding Walsh functions of the first paraiga (Rademacher functions) to the inputs of the elements 30 and 31. The calculation starts with the spectral coefficient C |. In block 5 of the control in this case, the output of the comparison circuit 11 is analyzed, and its further sequence of actions is determined from its state.

With the appearance of the output of the comparison circuit

0 II signal corresponding to the logical unit, the device calculates the smoothed value of the parameter (j) in accordance with formula (2). This is done on adder-subtractor 27, the spectral coefficients (first rank) are calculated, on the shear register 3, they are processed by the required number of bits, and on adder 4, the accumulation of shifted transformants is performed. The process ends with the calculation of the last p-th spectral coefficient and taking it into account in the total amount. At the end of the calculation on the adder 4, the binary code of the smoothed first derivative is generated. In the case "ate the value of C | did not exceed the set threshold (at the output of the comparison circuit 11 logical zero) the zero content of adder 4 is taken as the value of the parameter x (j), and the remaining spectral coefficients of the first rank are not calculated.

Having determined the value of the parameter t (), the device proceeds to the consideration of compensation for the second derivative. For this purpose, the shift register 3, adder-subtractor 27 and flip-flop 19 are zeroed out and the value of the second derivative is called to the adder-subtractor 27 from memory unit 1. Thereafter, the control unit 5 sends a signal to the counting input of the counter 16 and changes its state to "1, and the contents of the subtractor 27 are transferred to the shift register 3.

At the address corresponding to the given state of the counter 16, the value of the second derivative constant recorded therein is recorded from the RAM 1 block to the adder-subtractor 27. The device scans for performing the multiply operation, and the role of the subtractor 27 plays the role of the second shift register. The device uses a multiplication algorithm with a multiplier shift by higher bits forward. The content shift in adder-subtractor 27 is effected by signals from control unit 5 arriving at the fourth input of adder-subtractor 27. By the value of the high bit of adder-subtractor 27, arriving at unit 5, the final one generates control signals arriving at the adding bar adder 4. At the end of the multiply operation, a smoothed value of the first derivative is formed on adder 4. The latter is recorded in a memory cell t, the address of which is generated on the counter 16.

At the last stage of this cycle, the device calculates the smoothed value of the input signal. The control signals from the switch 29 are then removed. As a result, the generator 28 is disconnected from the inputs of the AND elements 30 and 31, and on the forward and inverse outputs of the switching unit 10 and the switch 29, levels are set equal respectively to a logical zero and a logical one. In accordance with this, a constant resolution is set on the AND 31 element, and the control signal arriving at the first inputs of the AND 30 and 31 elements passes only on the summation bar

adder subtractor 27. In block 9 of the formation of addresses, trigger 19 is set to one position, and the device begins to calculate the spectral coefficient of zero rank GO. After completion of the calculation process (after N clocks), the device takes into account the compensation for the first and second derivatives, and the resulting smoothed value of the input signal is fed to the main memory unit 1. The corresponding addresses are formed on the counter 16 of the address generation unit 9.

In subsequent cycles, the differential smoothing device works in a similar way.

Using the device allows to calculate the smoothed values of the input signal and its first two derivatives. Along with this, taking into account compensation for higher derivatives allows one to obtain smoothed values of the input signal and its first derivative without dynamic error. Doing an analysis of the input signal not by the magnitudes of the first and second derivatives, but by the corresponding spectral coefficients (i.e., until the first and second derivatives are completely calculated) and the practical elimination of the sample shift in the RAM block, due to the adopted addressing system, speed of operation of the differentiating and smoothing device.

Claims (3)

Invention Formula I. Differentiating-smoothing device containing a RAM unit, a Fourier-Rademacher spectral coefficient calculation unit, a shift register, an adder and a control unit, the device input being connected to the first information input of the RAM unit whose output is connected to the first input of the calculator Fourier-Rademacher spectral coefficients, the first output of which is connected to the first input of the shift register, the output of the shift register is connected to the first input of the adder, the output of which connected to the first output of the device, the outputs of the control unit from the first to the fifth are connected respectively to the second inputs of the adder, shift register and to the second, third and fourth inputs of the computing unit of the spectral coefficients of Fourier-Rademacher, in order to extend the functionality increase of speed and accuracy of work, blocks are entered into it, modulo two summation, address shaping, switching, two comparison circuits; The outputs of the control unit from the sixth to the tenth are connected respectively to five inputs of the address generation unit, two outputs of which are connected respectively to two control inputs of the operating memory block, the second information input of which is connected to the output of the adder, and the output to the second output of the device ; The eleventh output of the control unit is connected to the fifth input of the spectral coefficients calculation unit. The Fourier Ralimahor, the second output of which is modulo-two via a summation unit, is connected to the first input of the switching unit, the direct and inverse outputs of which are connected respectively to the sixth and seventh inputs of the Fourier-Rademacher spectral coefficients calculation unit; the second input of the switching unit is connected to the twelfth output of the control unit, three inputs of which are connected respectively to the outputs of two comparison circuits and the third output of the calculation unit of the Fourier-Rademacher spectral coefficients, the first output of which is connected to the inputs of two circuits. 2. Device by. I, characterized in that the modulo-two summation block contains (n - I) modulo-two adder groups; the first inputs of the adders modulo two of each group are combined and connected to correspond to one of the first (n - 1) bits of the n-bit input of the block, the second inputs of adders modulo two of each group are connected respectively to one of the bits of the n-bit block input, starting with a bit whose number is one unit higher than the group number; the output of each modulo two is connected to one of the m bits of the block output. 3. The device according to claim 1, characterized in that the switching unit contains m elements AND, elements OR, NOT; the first inputs of the elements AND are connected to the w bits of the first input of the switching unit; the second inputs of the And elements are connected to m bits of the second input of the block; the output of each element AND is connected to the corresponding input of the OR element, the output of which is connected respectively to the direct output of the block and the input of the element NO, the output of which is connected to the inverse output of the block. 4. A device according to claim I, characterized in that the address generation unit comprises a counter, a reversible counter, a decoder, and a trigger; moreover, the counting input of the counter, the counting and control inputs of the reversing counter, the single and zero inputs of the trigger are connected respectively to the five inputs of the block; the outputs of the counter and the reversible counter are connected respectively to the first and second inputs of the decoder; the single trigger output and the decoder output are connected to the first and second outputs of the address generation block, 5. The device according to claim 1, otherwise, CP) the Fourier-Rademacher spectral coefficients calculation unit contains an adder-subtractor, a Rademacher function generator, a switch, and elements , OR elements, one of which is connected between the forward output of the switch and the first input of the first element AND, the second element OR between the inverse output of the switch and the first input of the second element AND; the second inputs of the elements I are connected to the third input of the block, the outputs are connected respectively to the first and second inputs of the adder-subtractor, the third and fourth inputs of which are connected respectively to the first and fifth inputs of the block, the first and second outputs respectively to the first and third outputs unit, the fourth input of which is connected to the generator input of the Rademacher function, the output of which is connected to the second output of the unit on the first input of the switch, the second input of which is connected to the second input of the unit, the sixth and seventh in which rows are respectively connected to the second inputs of the first and second OR eleyentov. Sources of information taken into account during the examination: 1. USSR author's certificate number 355618, M.cl. G 06 f 7/38, 16.03.71. 2. USSR author's certificate number 377785, M.cl. G 06 f 15/32, 05.08.70. 3. Forward 2007207/24, M cl. G 06 f 15/32, 03/20/74, for which the decision to issue an author's certificate was made. -44 3f