SU607344A1 - Frequency divider with variable division coefficient - Google Patents

Description

The o7pofiCTBo contains a pelvite of 1 hour, consisting of H after each other akaschy counters, temporary rsh, shvliteli 2 and 3, the element OR 4 naeyevtov AND 5 - 7.

The input signal of frequency i is fed into the input bus of the frequency generator 1, you-ho {whose frequency / k is taken from the collectors of the transistors of the next GEero meter of the century counter. With divider I

Frequency of the two price output slots, which corresponds to the bullet state of the counting capacitor, counting and the zero state. These signals are sent to the input of temporary expanders 2 and 3, their outputs are connected through the element OR 4 with the first inputs of elements AND 5, to the second input of which the signal of the code for changing the coefficient of the VII counter is received. In addition, the output signal

the spreader 2 is fed to the first input of the AND 6 element, and the output of the spreader 3 is fed to the first input of the AND 7 element. The second input of the AND 6.7 elements receives the signal of the code for changing the division factor of the counter. The outputs of the And 5 elements are connected to the inputs of the decade low-order counter, and the outputs of the And 6.7 elements are connected to the inputs of the decade high-order counter.

The work of the frequency divider with a variable division factor is considered on the example of a three decade divider.,

If the input buses of the installation are counted, signals are sent out, then the de-f pulse 1 divides the input frequency by SOO, since the first decade counter counts the volvo and negative half-waves of the input voltage. The switching order of the triggers in the ten-day counter is shown in the table;

Claims (2)

The last column of the table shows the number of triggers and from which arms of these triggers (left or right) it is necessary to take a signal through an AND element with two inputs to determine the recorded digit. The output frequency of the divider is removed by the scalpers of the transistors of the first trigger of the third decade counter, the voltage of the output signal of the frequency f / 500 has a symmetrical shape. All the triggers of the decade counters are sequentially set to the positions corresponding to the digital outputs LLC, 999, 998 ..., 5O2 isOl, 500, 499. 498, "., 003, O02,) 001, Ltd., Nifra coincides with the supply of the half-voltage input voltage frequency-L to the corresponding colpo of the first ten-day counter. To set the division factors K 5OO, the signals of the code for changing the coefficient are assigned to the inputs of And 5, and to the inputs of the decade high-order counter, signals that through the And 7 element tend to put the ten-day counter into digital positions 4 - O, and through the And 6 element - respectively, in the Digital position 9 - 5, for example, when the division factor 499 is set to And 5, the first and second decipher signals are fed to the input buses. On elements 6.7 of the third decade of the decade, the signal also goes to the input bus. At the arrival of the input half-wave of the voltage of the frequency f, to set the zero state of the divider 000, a signal appears at the output of the temporary expander 2, the result of which is the first 9 in the first decade and the figure 9 in the high decade number 9, therefore until the figures 50O, when the first trigger of the third decade is in the OZ position (see table), passes 499 half-waves of the first output frequency. When the number 500 appears, the signal at the output of the expander 3, through the element I 5 in the first two decades, set the number 9, and through the element I 7 in the highest decade the number 4, so to the LLC number, when the first trigger of the third decade divider is in 30, also passes 499 half-waves of the input frequency. Thus, the output frequency is 1/499, and the output signal of the voltage of this frequency is strictly symmetrical, ffrf at equal half-waves of the ripple voltage. The operation of a frequency divider with a variable division factor for any division factors up to 1 occurs in a similar way, and the output voltage signal always has a strictly symmetrical form. The invention The frequency divider with a variable coefficient of healings, which contains successively connected decade counters, the first input of which is connected to the input bus, and the AND elements, which are different from the fact that, from the whole possibility of obtaining a symmetrical output signal, time expanders and the element are entered into it OR, at the same time, the inputs are connected to the inputs of the decadent counters of the previous bits. And, the first inputs of which are combined are connected to the output of the OR element, the inputs of the latter are connected via a time expander to the digital outputs of the decompression counters, and the inputs of two other elements AND, the first inputs of which are connected to the outputs of the time extenders, are connected to the inputs of the older counter. the second inputs of the Bcex elements And are connected to the source of the code for changing the division factor. I fcTO iBBKB information taken into account during the examination of l.StettKOHtc fHg4 "i" tf.A, vaf oibEealif Fredu tcydividek Usittrf rfticKoSoic eEemeKia ,, l96r, "4-ra, p4l9-426. 2. USSR author's certificate No. 3tl268, cl. 06 P 7/52, 05.27.69. one . . . IZZJ