SU607281A1 - Storage with error correction at information readout - Google Patents

Description

I

This invention relates to the field of storage devices.

Storage devices with error correction in reading information are known, containing an information control block connected to a control block and a random access memory connected via a reproducing block and a control unit for verifying information to the number register executed on triggers with a counting input {.

In this device, information is stored in the form of error-correcting code, containing informational and control information: bits. After reading a word, the information accuracy control block forms control bits from information bits and compares them with stored control bits; in the case of the inequality of the formed and stored congresses, the information accuracy control unit generates a correction signal, which translates the corresponding number register trigger to the opposite state.

However, the known device requires performing a series of logical operations on the information and control bits of the stored information, which complicates it.

The closest in technical essence to the invention is a memory device with error correction when reading information containing a register of numbers divided into groups, a drive whose inputs are connected to the outputs of the writing drivers and the address block, amplifiers counting, the coding block with the input register, the formation block control code, fault address decoder, error correction block, output register (2J.

In this device, the excess, check bits of the Hamming code are added to the number received on the register by means of a co-block. After reading the information stored in the Hamming code, the decoder block from the information private word again forms check bits; read and newly formed probes are compared by a control code generation unit; The resulting comparison code pushes the input to the malfunction address decalitator, which gives a signal on the output bus with the same number as the defective bit, in the error correction block, the information is inverted in the malfunctioning bit, and the corrected information is set on the output register .

However, this device, like the previous one, requires performing a series of logical operations on the recorded and readable information and contains in this connection a number of complex logical blocks, which complicates the device and reduces its speed.

The aim of the invention is to simplify and improve the speed of the device.

This is achieved by the fact that the proposed device contains decryptors, encoders and input and output combinatorial switches according to the number of number register groups, the inputs of the decoder are connected to the corresponding outputs of the number register, and outputs to the inputs of input combinatorial switches, the outputs of which are connected to the inputs of the recording drivers, the inputs of the output combinatorial switches are connected to the outputs of the storage device, and the outputs to the inputs of the read amplifiers, the outputs of which are connected to the inputs of the corresponding encoder in.

FIG. 1 is a block diagram of the described device; in fig. 2 is a diagram of a linear transformer combinatorial switch with a summation of voltages, as well as input and output impulses for its operation.

The device contains a register of the number 1, divided into groups, for example, two bits in each. The outputs of two bits 2i and 2 of this register, belonging to the same group, are connected to the inputs of the decoder 3. The outputs of the deflector are connected to the inputs of the input combinatorial switch. 4. made, for example, in the form of a linear transformer combinatorial switch with voltage summation, the circuit which is shown in FIG. 2. The outputs of the input combinatorial switch are connected through the write drivers 5, 6, 7, 8 to the corresponding bits of the record of drive 9 (it is preferable that the storage elements of the drive have read signals «1 and различ O, differing by polarity). The output tires of the accumulator belonging to the same group of stored information are connected to the inputs of the output combinatorial switch 10, similar to the combinatorial switch 4. The outputs of the combinatorial switch 10 are connected via read amplifiers 11, 12, 13, 14 to the inputs of the encoder 15 that converts the unitary code (" 1 of p) to binary, 2-bit. Similar block connections have been made for all of the ocular groups (pairs) of bits (not shown in the drawing).

The address unit 16 includes the hardware necessary to receive the address code, decrypt it, and generate a drive access pulse through the corresponding coordinate women; its outputs are connected to the address tires of the accumulator 9.

If the drive 9 is built from memory elements with a. Amplitude discrimination of the signals “1 and“ O, then between its outputs and the inputs of the output combinator switch 1

bodies 10, it is advisable to include a converter of unipolar signals into bipolar (not shown).

Consider the operation of the device on the example of a ferrite memory device built on a 2D system with two cores per bit. The information to be written to the drive 9 is received in the usual binary code into the register of the number 1, divided into groups, for example, two bits each .

0 The two-digit code from the outputs of the corresponding bits 2 and 2 of the register of the number 1 determines the number of the selected output bus of the decoder 3. An impulse from this spike is fed to the corresponding terminal of the input combinatorial switch 4 having four inputs

5 and exit. For definiteness, we consider a linear transformer combination switch, the circuit of which is shown in FIG. 2. In this case, the impulse from the selected length of the decoder 3 is applied to one of the

0 output windings 17 switch. Due to the reversibility of the switch, when a pulse is applied to one of the output windings, impulses appear on the input windings 18, the polarity of which corresponds to the signs of the members of a specific row of the Hadamard matrix (in Fig. 2

5 shows pulses on the input windings of the switch corresponding to the second row of the Hadamard matrix). The pulses from the outputs of the input combinatorial switch 4 are amplified to the required amplitude by the writing drivers 5, 6, 7, 8 and fed to the corresponding four drive sections 9. Thus, the two-digit code from the register of the number 1 is written into four storage cells of the drive; however, there is no one-to-one correspondence between the bits of the written two-bit code and the storage cells of the storage device; all four memory cells store information on two bits of the code being written as a combination of numbers corresponding to a specific row of the Hadamard matrix.

When reading signals from the four storage cells in question

9 are supplied to the inputs of the output combinatorial switch 10, since the read

the signals are approximately equal in amplitude, and their polarity corresponds to one of the rows of the Hadamard matrix (since in the device under consideration the signals "1 and O differ in polarity), then the corresponding output of the combinatorial switch 10 shows the total signal,. which is equal to the quadruple amplitude of each of the read signals from the storage cores. At the same time, there are no signals at all the other outputs of the combinatorial switch 10. A summing signal from the output of the switch

10 is amplified by an appropriate read amplifier (11, 12, 13 or 14) and is fed to the input of the encoder 15, which converts the unitary code to binary, i.e., the P1 encoder 15 performs the inverse decryption operation. The output of the encoder 15 is two-digit

i-- -х „- (code. coinciding with the previously recorded at this address.

tai device works in the absence of errors. If an error occurred while reading the information due to a failure of the core of the drive 9, or a broken output bus, or a break in the write bus of the drive, etc., then one of the inputs of the combinatorial switch 10 will not have a pulse. However, as can be seen from the analysis of the diagram of FIG. 2, this will not lead to the loss of all or even part of the information recorded in the four cells of the accumulator in question. The signal on the selected bus of the combinatorial switch 10 is reduced by one, and on unselected tires, the interference is ± 1. In the worst case, the signal-to-noise ratio will be three, which is quite enough to reliably distinguish them. Failures of some elements of combinatorial switches are also permissible.

TaKH.v way, with a total number of bits, equals m -2-. , it is allowed - errors without malfunctioning the device as a whole, where n is the number of bits in the recorded numbers, and k is the number of bits in the group. In this case, the redundancy in the number of bits of the device is 2 k; at l: -2 27k 2. For evaluating the effectiveness of describing my device. You compare it with the device in which information is stored in the Hamming code with the correction of one error.

Let p 3b, k 2, then the described device should have 72 bits and at the same time 18 errors can be corrected. If, however, the device uses (7.4) - Hamming code, then it should be divided into 9 groups of 4 information bits in each and have only 63 bits, but only 9 errors can be corrected. Thus, on the device. My device with almost the same redundancy is 2 times more effective in terms of corrective ability.

The necessary redundancy in the described device can be significantly reduced by using commby on rotary switches.

with the number of outputs in excess of the number of inputs. For example, to correct one DI for 4 outputs, 3 inputs are enough, for 8 outputs 4 inputs, etc. The number of required storage elements in a group is reduced accordingly: 3 for storing two binary bits. 4 - for storing three binary bits, etc. Combinatorial 1e switches do not give rise to interference on the unselected outputs, however, the visibility of the signal against the background of these lines is quite high and is determined by the minimum code distance between the lines. mbina.torno1s switch

15

Claims (2)

1. Author's certificate number 333065 cl. ATP 29/00, 1970. 2.Sb. "Actual issues of technical cybernetics," Science, M., 1972, p. 235-240. rz t.i. yy Ll GI i G I shishi . . l GT1 1, .  -U- L