SU579659A1 - Self-checking memory - Google Patents

Description

I

The invention relates to the field of storage devices (memory).

A self-monitoring storage device containing a test bit drive, a fault detection unit, AND and OR elements is known. The disadvantage of this device is low Scalability.

The closest technical solution to the invention is a storage device itself: a control containing a drive connected to the receiving and receiving units, the address code sensor and the control unit, delay elements, AND and OR elements and the switching unit. However, this device does not adapt to the nature of the failure. This reduces the effective capacity of the device, and also causes the entire device to fail in case of group failures of the elements of dy in the numerical cells of the storage device, which reduces the reliability of the device.

The aim of the invention is to increase the reliability and effective capacity of the device.

The goal is achieved by the fact that in the proposed device the first control output of the accumulator is connected via the first delay element to the input of the number output unit and directly to the control input of the switching unit, the setup input of which is connected to the sensor input to the address. The outputs of the switching unit are connected to one input of the And elements, the other inputs of which are connected to the output of the control unit. The output of one of the elements AND is connected via the first element OR to the inverse input of the block; receiving numbers and to the first control at the entrance to the drive. The output of the other element Vment AND is connected via the second delay element and the second element OR to the input of the address code and directly to the VTOR1L4 control input of the accumulator, the second control output of which is connected to one of the inputs of the second OR element through the third element of the OR.

The drawing shows a structural scheme of the proposed memory.

The device contains a block for receiving numbers 1, a drive 2, in which there are two control bits, an address code sensor 3, a number output block 4, a control unit 5, the first 6, the second 7 and the third 8 delay elements, And 9 elements and 10, a switching unit 11, the first 12 and the second 13 elements OR, the input head 14, the address change bus 15 and the input bus 16.

The first control output 17 of the accumulator (connected to the first control discharge of the accumulator) is connected via the delay element b to the input 4 and directly to the control input of the unit 11, the installation input k6 is connected to the input of the sensor 3. The outputs of the unit 11 are connected to one the inputs of the elements 9 and 10, the other inputs of which are connected to the output of block 0 | ka 5, the output of the element 9 and 9 through OR 12 are connected to the inverse input of block 1 and directly to the first control input 18 accumulator 2, the output of the element 10 through the delay element 7 and the element OR 13 connected to, input of sensor 3 and directly with the second control 19 of the accumulator (associated with the second control discharge of the accumulator) | the second, the control output 20 of which through the delay element 8 is connected to one of the inputs of the element OR 13. i The device works as follows /

From / the reception of the numbers 1, the code of the number enters the drive 2 and is written to the address set by the sensor of the address code 3. After writing the ETs test read of this code and comparing the writeable AND of the read code in the checkout block. five.

In the absence of a match, which indicates a malfunction in the numerical cell of accumulator 2, a signal is generated at the output of block 5, which is fed to one of. inputs of elements 9 and 10, to the other inputs of which control signals from the outputs of block 11 (for example, a trigger) are set, which are reset to the initial state by a signal that is fed to the input of the sensor of the address code 3.

In the initial state, block II is issued, ieT, allowing the signal to the AND 9 element and prohibiting the signal to the AND 10 element. In this case, the signal from the control unit 5 goes to the output of the AND 9 element, through the OR 12 element to the inverse input of the number 1 receiving unit, inverts the code of the number to be written and, together with the invertible code of the number, is written to

in the first control list

The number of storage devices is 2 at the address.

After writing the inverted: code, the control reads and compares the read code with the code of block 1;

In the absence of a match, which indicates the malfunction of the memory cell at the polled address and the impossibility of its elimination by inverting the written code, the output

The control unit 5 forgets the signal, which, as in the first case, arrives at the inputs of the And 9 and 10 elements.

This signal arrives at the output of the AND 10 element, / to which the permitting signal from the block 11, which is set to a new state by the signal from the output 17 of the accumulator 2, arrives. From the output of the And 10 element, the signal g is recorded as the second check digit of the accumulator 2 at the requested address and through the delay element 7 is fed to the input of the sensor of the address code 3, thus changing the address code. In this case, the signal coming from the output of the delay element 6 through the OR element 12 to the inverse input of block 1 returns the code of the number to the initial state.

At the new address, the write access is the same.

The transition to the record of the new number is carried out in the absence of a signal at the output of the control unit 5 in the mode of control reading.

In the information reading mode, when a memory cell is accessed, in which the malfunction has been resolved. By recording the recorded code, s in block 4, the code of the number is restored by inverting it with a signal from the output 17 of accumulator 2 via the evil delay element 6

When accessing a memory cell in which the malfunction is not resolved by inversion, the output 20 of accumulator 2 generates a signal that enters through delay element 8 and element OR 13 at the input of the address code sensor 3, changes the address and thus bypasses the failed memory cell ti with

The described memory has higher reliability indices as compared with the known device (since, in addition to correcting a single failure in a numerical memory cell by inverting the number to be written, a bypass of the memory cell is also provided, in which the malfunction cannot be eliminated above method.

In this case, the backup storage capacity is used optimally. . .

Claims (2)

1. Author's certificate of the USSR) 367460, Moscow, 6 11 C 29 / 00,1971. 2. Authors certificate of the USSR 497639, M. class. G 11 C 29 / 00,1973