SU572923A1 - Frequency-to-code converter - Google Patents

Description

one

The invention relates to a pulse technique.

A frequency converter into a code comprising a reference frequency generator, an auto-shift generator, a modulator, a filter, a voltage controlled oscillator, a converter, a comparison element, a frequency converter into a voltage, and triggers 1 are known.

This converter is complex.

The closest to the claimed technical entity is a frequency converter into a code containing two reference frequency generators, the output of one of which is connected to one input of a controlled frequency divider, and the output of the other through a synchronization unit connected to another input of a controlled frequency divider, input the memory register and through the delay element with one key input, the other input of which is connected to the output of the controlled frequency divider, where the outputs of the memory register are connected in parallel with the inputs of the controlled sharing tel frequency 2.

The disadvantage of this converter is the lack of speed.

In the case of speeding up the frequency converter into a code containing two reference frequency generators, the output of one of which is connected to one input of the controlled frequency divider and the output of the other

through a synchronization unit connected to another input of a controlled frequency divider, input of the memory register and through a delay element with one key input, the other input of which is connected to the output of the controlled frequency divider, and the outputs of the memory register are connected bitwise to the inputs of the controlled frequency divider , introduced two counter-register and a logic element for comparing codes. Moreover, the inputs of the first register register are connected to the second output of the reference frequency generator and the output of the delay element, its outputs are connected bitwise with the inputs of the memory register and logic element for code comparison, the output of which is connected to the corresponding key input, and the inputs of the second counter register are connected respectively with key output and delay element output.

The structural electrical circuit of the converter is shown in the drawing.

The converter contains the generators 1 and 2 of the reference frequency, the synchronization unit 3, the element delay 4, the controlled divider

5 frequencies with a fractional division factor, memory register 6, counters-registers 7 and 8, a key 9, a logic element 10 for comparing codes. The input signal is input 1I, the number code is input 12, the signal is input 13

Claims (2)

the code corresponding to the smallest measurement period, the output signals are removed from outputs 14 and 15. The converter operates as follows. The next i-th pulse of the converted frequency FX is fed to the input 11 and then to the input of the synchronization unit 3. The pulse from the output of the synchronization unit writes the number from counter-register 7 to register 6 and resets the counter of the controlled divider 5. This same pulse, having passed through delay element 4, resets the counters-registers 7 and 8, and also opens the key 9. After the end of i The -ro pulse of the converted frequency FX to the input of the controlled divider 5 receives the reference frequency e, to the input of the counter-register 7 - the RE frequency, and through the public key 9 to the input of the counter-register 8 - the frequency / d from the output of the controlled divider. FF k / 7 LfL el - j - m "dJVt where k is a constant chi-layer whose code is set at input 12. The key 9 is closed by a signal from the output of element 10 when the number in the counter-register 7 is equal to the number code set at input 13 Thus, the number of NX pulses is fed to the input of the counter-register 8 for the time between the pulses of the converted FX frequency. N, where Dg - - After obtaining the result of the conversion in units of frequency, it is necessary that equality takes place. kN, .lQ% a to ensure the normal operation of the controlled divider 5, the number k must not exceed the number With the arrival of the (f-fl) -ro pulse of the converted FX frequency in register 6, the number N - is rewritten (from counter-register 7, controlled the divider and counters-registers 7 and 8 are reset, the key 9 is opened and the converter operation cycle is repeated. The transfer ratio of the controlled divider changes from "/ 2 to / 4" when the period of the frequency to be converted from Gmin to T. max. The output of the controlled divider is not lower than F in, / 4. This allows the instantaneous frequency value to be determined from the measurement result of each period, which improves its speed.A invention The frequency converter into a code containing two reference frequency generators, one output of which is connected to one input of a controlled frequency divider, and the other output through a synchronization unit connected to the input of the controlled frequency divider, the input of the memory register and through the delay element with one key input, the other input of which is connected to the output of the controlled frequency divider, The memory register outputs are connected bitwise with the inputs of a controlled frequency divider, characterized in that, in order to improve speed, two counter-registers and a logic element are introduced for comparing codes, and the inputs of the first counter-register are connected to the second output of the second the reference frequency generator and the output of the delay element, its outputs are connected bitwise with the inputs of the memory register and the logic element for comparing the codes whose output is connected to the corresponding key input, and the inputs of the second counter a-register connected respectively with the output key and output of the delay element. Sources of information taken into account during the examination 1. Japan Formation No. 42-3781, cl. 97 (7) E416, 13.02.69. 2. Author's certificate number 263299, cl. G 06 3/18, 14.02.69.