SU558277A1 - Device for diagnosing malfunctions of peripheral devices - Google Patents

Description

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The invention relates to digital computing and can be used for program control and preventive maintenance of digital computer systems containing software control and fault diagnosis tools.

A device for monitoring I / O channels of digital computers is known, which contains code points of a symbol, control lines, a block of interaction with a digital computer channel, an information register, a block to simulate modes, and a block of information generation. This device allows in stand-alone mode to perform the adjustment and verification of I / O channels without connecting real external devices and indicating faulty situations both in one-shot mode and in cyclic mode. However, it does not allow monitoring and troubleshooting of peripheral devices. Another drawback of the device is the low resolution capacity by addresses and time, as it allows reading only the state of a small number of storage elements and does not allow interrupting the operation of the peripheral device at intermediate points of the time exchange diagram, which significantly reduces the time resolution.

The closest to the technical essence of this invention is a device for diagnosing faults, containing a block of PI elements, the first input of which is connected to the output of the memory unit of the peripheral device, and the output is connected to the input of the exchange register, the output of which is connected to the first input of the switching unit, the second the input of the switching unit is connected to the first output of the control unit, and its output is connected to the input of the exchange register of the peripheral device; the second output of the control unit is connected to the second input of the unit of elements AND.

A disadvantage of this device is the low resolving power but time and the impossibility of using the existing communication lines between the digital computer and the non-peripheral device. Another disadvantage of the device is the lack of means for scaling time in time management. Necessity of this

the changes are due to the presence of both high-frequency and low-frequency processes during the operation of the peripheral device.

The aim of the invention is to increase the efficiency of monitoring peripheral devices.

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To do this, a mode decoder, a time control unit, a register number decoder, an amplifier unit and an input switch are introduced into the proposed device, the second exchange register output connected to the mode decoder input, the output of which is connected to the first control unit input, the third exchange register output connected to the first the input of the time control unit, the second input of which is connected to the third output of the control unit, the third input - to the communication output, to the external environment of the driver device, the fourth input - to the blocking switch, the output of the peripheral device, the first output of the time control block is connected to the third input of the I block, the second output is connected via the register number decoder and the amplifier block to the fourth input of the AND block, the fifth input of the KOTQ interface, the third output of the time control unit is connected to the first input of the fixation unit, the second input of which is connected to the controller, its peripheral device output, and the output to the second input of the control unit and to the communication input from outside The first output of the input switch is connected to the control input of the peripheral device, the second output is connected to the third input of the control unit, the fourth input of which is connected to the output of the clock pulses of the peripheral device, the output of the switching unit is connected to the information output of the peripheral device .

In addition, in the proposed device, the time control unit contains two - counters, two OR elements and five AND elements, the overflow output of the first counter is connected to the first input of the first AND element and through the first OR element to the second counter input, the overflow output of which is connected to the second input of the first element And with the first input of the second element And, the second input of which is connected to the first input of the third element And, and the outputs of the second and third elements And through the second element OR connected to the input of the first account Linda, the second input of the first OR gate connected to the output of the fourth AND gate having an input coupled to the input of the fifth AND gate, whose output is via a second OR gate connected to the input of the first counter.

This makes it possible to substantially increase the depth of localization of faults of peripheral devices due to the possibility of stopping the operation of the peripheral device at an arbitrary cycle and reading the state of its storage elements.

FIG. Figure 1 shows the structural scheme of the device proposed along with the symbolic scheme of the peripheral device, which allows us to illustrate the structural

connections between these devices, in FIG. 2 is a block diagram of a temporary coitrol block.

The iperia device 1 contains a peripheral device control unit 2, a control unit 3, a peripheral device exchange register 4, a peripheral device memory unit 5. The peripheral device 1 communicates with some external environment using the communication unit 6 with the external environment, which operates under the control of the communication unit control unit 7. In particular, if we refer to a punched tape input device under a peripheral device, block 6 moves the punched tape, searches for the required array, reads information, etc. Block 7 performs a tape drive start, reversing and stopping. Peripheral device (PU) also

It includes a clock pulse generator 8 and a blocking unit 9. The output signals of the blocking unit 9 are fed to the control unit 2 by the peripheral device. When a blocking signal is received,

node lock 9 stops the electronic part of the PU,

The output signals of the memory block 5 and the register of the memory 4 are fed to the corresponding inputs of the block of elements AND 10, the outputs of which are connected to the installation inputs of the exchange register 11, which is a full-digit shift register. The outputs of a certain group of bits of this register are connected to the inputs of the mode decoder

12, the output of which is connected to the input of the control unit 13, which is connected with all the units of the device and implements the testing of all its modes of operation. Another group of bits shift register 11 is connected to the inputs

temporary control unit 14. The output of the rightmost bit of the exchange register I is connected via the switching unit 15 to the inputs of the exchange register 4 of the peripheral device, as well as to the information inputs 16

Digital computer The output of the control circuit of the peripheral device 3 and the overflow output of the time control block 14 are connected to the inputs of the fixation block 17, the output of which is connected to the input of the block 7 of the control block

connection, blocking the input of the blocking unit 9 and the input of the control unit 13. The output of the fixing unit 17 is also connected to the bus signal of the malfunction 18, through which the malfunction signal (CH) enters the digital computer.

The outputs of the temporary control unit are connected to the inputs of the decoder 19 of the register number, the output of which is connected to the input of the amplifier unit 20. The outputs of the amplifier unit 20 are connected to the inputs of the AND 10 element unit. The input switch 21 is connected to the device input.

Pa figs. 2 shows a block diagram of a block.

time control This block contains

two counters 22 and 23, the signals on the counting

inputs which come through the elements OR 24 and 25.

The inputs of the element OR 24 are connected to the outputs of the elements AND 26-28. The output of the element 29 is connected to the input of the element OR 25. The output signal of the time control unit is formed at the output of the element 30. The state of the counters 22 and 23 is established via the bus 31 by rewriting the status of the bits of the exchange register 11. and 23 connected to the inputs of the block elements And 10.

The proposed device works as follows.

From the digital computer to the input switch 21 enters the address word along with a set of control signals in accordance with the time exchange diagram adopted in the system. The control unit 13 contains known means implementing an exchange with a digital computer, as a result of which the address word enters the exchange register 11, and the response signals given on the temporary exchange diagram are output to the digital computer. This, depending on the state of the internal triggers of the control unit 13, the input switch 21 transmits the control signals coming from the digital computer either to the exchange register 11 or directly to the peripheral device 1. In this case, the exchange takes place between the digital computer and the peripheral device after receiving a certain address word, it starts working out the mode prohibited by the digital computer.

After accepting the exchange register and the address word, the forced operation is deciphered using the mode decimator 12, which activates the control unit 13 accordingly.

The proposed device has several modes of operation.

Mode of preparation. In this mode, after receiving the address word and decoding the required operation mode, the control unit 13 carries out a parallel transmission of the code of the address part of the address word to the counters 22 and 23 of the time control unit 14. In addition, some triggers of the control unit 13 are triggered and the blanking of the control unit is performed. In addition to the control and address parts, the address word contains bits of the signs that determine the type of pulse signals used to fill the counters 22 and 23 of the time control unit 14. From the peripheral device 1, the device for diagnostics of peripheral devices receives pulses of the clock signal 8 transmitted through interlock node 9. These signals are high frequency base frequency signals used in the applied cell system. In addition to this frequency, low-frequency signals from the control panel are received in the control panel either electronically or electromechanically. In the last

In this case, these signals can be received in block 6 of interaction with the medium.

An example of such pulses may be sync pulses when moving punched tape or slower signals — signs of arrays on a data carrier. In the specific implementation of the device, two bits of the address word denoted T1 and T2 are used to set the frequency type. The outputs of these bits of the exchange register 11 enter the temporary control unit 14 and open the corresponding circuits in it. This completes the preparation mode. The control unit 13 notifies the digital computer about the end

exchange mode. A universal way of notifying the end of the Exchange is to issue a fault signal to the digital computer.

The mode is working. After receiving the fault signal, the digital computer that implements the diagnostic program organizes one of the working exchanges with the control center. In this case, the control information coming from the digital computer via the input switch 21 is sent to the corresponding circuits of the peripheral device, which receives the address word and tests the mode in the same way as it does in the working relays without using the proposed device. However, according to one of the first control signals of this exchange (for example, “Address address”), the control unit outputs the permit potential via the bus 32 and simultaneously with the working mode in the control panel, over the buses 33 and (or) 34 according to the type of frequency used to the counters 22 and (or) 23 impulses begin to flow. The overflow signal that occurs at the output of the element And 30, passing through the fixation block 17 causes the PU to stop working by sending a signal to the node 9

blocking the frequency and the signal “Stop to block 7, which stops the movement of the mechanical blocks of the peripheral device. In addition, this signal reset the control unit.

13 and enters the digital computer as a fault signal for notification of the end of the exchange. If during the time of working out the mode in PU, which may contain defective elements, a malfunction signal arises in

If the peripheral device control unit 2 or it is fixed in the control unit 3, then after passing through the fixing unit 17, it causes the same effects as the overflow signal of the time control unit 14 counters.

Let us consider in more detail the work of this unit. Signals T1 and T2 define three fill modes for counters 22 and 23. In the first two modes, both of these counters are combined into

one counter of higher bitness. The combined counter is filled either by high-frequency signals coming through bus 33 (code T1-T2 01) or low-frequency signals coming in

on the bus 34 (code T1-T2 10).

In the first case, the pulses pass through the elements AND 27 and OR 24 in the presence of a resolving potential on the bus 32. The overflow signal of the counter 22 through the OR element 25 enters the input of the counter 23. The output signal on the And 30 element is formed after the overflow of the counter 23, set to 1 of its most significant bit and repeated overflow of the counter 22.

In the second case, the operation is similar, with the only difference that the pulses pass through the element 28.

In the third case (code T1-T2 I), the signal at the output of the element And 30 appears after a certain number of high-frequency pulses, after a certain number of low-frequency pulses have passed. In this case, the pulses from the bus 34 pass to the counting input of the counter 23 through the elements AND 29 and OR 25, if present, and its potential on the bus 32. After the counter 23 is full, high-frequency pulses on the bus 33 begin to pass to the counting input of the counter 22 26. The overflow signal of this counter will cause the output of the output signal.

Read the status of the PU. After receiving the malfunction signal, the diagnostic program organizes a cycle of exchanges of the third mini-exchange of reception of information on the state of the PU in the digital computer at the time of overflow of the time control unit counters or the generation of a fault signal in the PU. In these modes, the address-command is again through the input commentator 21 enters the exchange register 11, since the control unit has been reset. The operating mode code is decrypted by the decoder of the modes 12, which excites the control unit 13, as a result of which the contents of the address bits of the exchange register 11 are written to the time control unit counters 14 and decrypted by the register number decoder 19. The potentials of almost all PU triggers are connected to the block of elements I through special connectors. The PU registers are also connected to these elements, as well as control triggers that are coded into dummy registers. The register number decoder determines the number of the requested register DVR and excites the corresponding amplifier in the amplifier unit 20, which overwrites the contents of the dummy register into the I register. After that, the control unit 13 switches to the output mode of the register 11 in the DVR. The output is made by shifting the information in the register, and the information being pushed through the switching unit 15 enters the digital computer. Since the information provided does not contain check digits, the exchanges of this type must be made with the control locked. The exchanges of the third type are carried out as many times as there are addressable registers, with each time the number of the register is changed.

Upon receipt of a fault signal from the control center, the contents of the time control circuit 14 may be useful for localizing the fault. For receiving this information, a special mode is provided in which the address part of the register 11 is not copied to counters 22 and 23, but rather the contents of these counters are not recorded in the register exchange 11 and

The mode of issuing information in the digital computer is turned on. In order to reduce the number of elements in block 10, it is possible to transmit between registers of PU in the event that the equipment for such transmissions is contained in

PU

In many PUs, such as display panels, printing devices, various actuators, there is a memory whose output signals are no longer output.

the registers available for the digital computer, and directly nodayutsya on output elements. To increase the completeness of the control of such devices, a special group of elements within the block 10 is provided for

receive pulse signals. The verification of the generation of these signals is carried out at the end of the diagnostic program and it is assumed that the exchange part of the control center has already been tested and is working correctly.

The exchange of the first type in the test mode of the pulse signals is similar to that described above, except that the control unit 13 supplies the enabling potential to the receiving elements of the pulse signals and supplies the control potential to the switching unit 15. The exchange of the second type proceeds exactly as described, t that is, an exchange between a digital computer and a PU is essentially organized. During the development mode in PU occur

pulses that are recorded on the exchange register 11. The third type of exchange is conducted with the register number corresponding to the exchange register 4 of the peripheral device. When entering the address-command in the register 11

put forward bits through the switching unit 15 are pushed into the exchange register 4. Then, during the processing of this mode, the contents of register 4 are transferred to the register I and output to the digital computer.

Thus, the proposed device allows stopping the PU operation on any clock cycle and reading the state of almost all storage elements, i.e. the resolution of the addresses and over time using the proposed device becomes as high as in a digital computer. At the same time, during the diagnostics of PU, there are practically no problems of self-diagnostics, i.e. the draw system is small. In addition, it is possible to memorize some impulse signals and output the received word in a digital computer. At the same time, an insignificant amount of additional equipment is spent in the PU (building input depots for some short signals and outputting

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memory elements). By slightly complicating the design of the PU, it is possible to eliminate the need to disconnect the working connectors of the PU.

This opens up possibilities for creating effective diagnostic programs for peripherals with a localization depth to a single signal circuit.

Claims (2)

1. A device for diagnosing malfunctions of peripheral devices, which contains a block of elements AND, a nerve input that is connected to the output of the memory unit of the peripheral device, and an output is connected to the input of the exchange register, the output of which is connected to the first input of the switching unit, the second input of the switching unit. with the first output of the control unit, and its output with the input of the exchange register of the peripheral device, the second output of the control unit is connected to the second input of the AND block, characterized in that, in order to increase the efficiency control device of a peripheral device, a mode decoder, time control unit, register number decryptor, amplifier unit and input switch are entered into the device, the second output of the exchange register is connected to the input of the mode decoder, the first output of which is connected to the first input of the control unit, the third exchange register output is connected with the first input of the time control unit, the second input of which is connected to the third output of the control unit, the third input to the output of communication with the external environment of the peripheral device, four the input is with a blocking output of the peripheral device; the first output of the time control unit is connected to ten the third input of the And block, the second output through the register number decoder and the block of senders are connected to the fourth input of the And block, the fifth input of which is connected to the output of the peripheral exchange register, the third output of the time control block is connected to the first input of the fixing block, the second. Which is connected to the controlling output of the peripheral device, and the output to the second input of the control unit and to the communication input to the external environment and to the blocking input of the peripheral device, the first output input second switch coupled to the control input of the peripheral device, the second output - to a third input of the control unit, the fourth input of which .soedinen yield clock peripheral output switching unit connected to data output peripheral device. 2. The device according to l. 1, characterized in that it contains a temporary control unit / contains two counters, two elements OR, and And the elements And, the output of the overflow of the first counter, is connected to the first input of the first element And And through the first element OR to the input of the second counter, the overflow output of which is connected to the second entrance of the first element And, and to the first input of the second element And, the second entrance of which is connected. n the first input of the third element is AND, and the outputs of the second and third elements are AND through the second element OR connected to the input of the first counter, the second input of the first element OR is connected to the output of the fourth element AND whose input is connected with the input of the fifth element AND, the output of which through the second element OR is connected to the input of the first counter. AOTL