SU1156078A1 - Device for exchanging data between controlled object and electronic computer - Google Patents

Abstract

DEVICE FOR THE EXCHANGE OF INFORMATION TO THE POLE OF CONTROL AND. ELECTRONIC COMPUTING MACHINE containing a buffer memory, the address inputs of which are connected to the counter output, a bi-directional switch, the first group of information inputs-codes of which is connected to the group of information inputs-outputs of the control object, and the second group of information inputs-outputs with a group of information, address and control buses of an electronic computer, a memory adapter, characterized in that, in order to reduce the equipment, the device comprises a control mode setting unit, a unit memory management register mode, and the memory management unit contains a decoder, elements NOT, AND-NOT, the first and second outputs of the decoder are connected to the first inputs of the first and second elements AND, the second inputs of which are connected to the third output of the decoder, and the outputs - the first inputs of the third and fourth elements NAND, respectively, whose outputs are connected to the first and second inputs of the fifth element NAND, whose code is connected to the first input of the sixth element NAND, the outputs of the first and second elements are NOT connected to the first and the second inputs of the seventh NAND element, the output of the second element is NOT connected to the second inputs of the third and fourth NAND elements, the output of the third element is NOT connected to the Third input of the fourth NAND element, the output of the second NAND element and the output of the fourth element connected to the first and second inputs of the eighth element AND-NOT, the output of which is connected (L nen with the third input of the fifth element AND-NOT, the fourth input of which is connected to the output of the ninth element AND-NOT, inputs connected to the outputs of the fifth and sixth elements NOT, the outputs are sixth About and the seventh elements of the NAND are connected to the first and second inputs of the tenth element of the NAND, the output of which is connected to the first input of one Oi of the eleventh element of NAND, the second and about the third inputs of which are connected respectively to the output of the sixth element NOT and quarter the output of the decoder, the inputs of which are connected to the outputs of the bits for selecting the type of control information of the mode register, the inputs of the first, second, third and fourth elements are NOT connected respectively to the read and write outputs of the group of control output buses constant computer, the outputs of the sixth, seventh and de of AND-NO elements are connected respectively to record inputs.

Description

read and write lock of the buffer memory; the output of the sixth element is NOT connected to the gate input of the fifth element NOT and the fourth input of the eleventh NAND element, the output of which is connected to the counting input of the counter, and the control setting unit contains four triggers, AND elements, AND-NOT, AND-OR-NOT, S-input of the first trigger and the first input of the first element AND are connected to the total reset of the device, C-input of the first trigger is connected to the output of the NAND element, and its R input and D input the third trigger is connected to the outputs of the bits of the mode By locking the mode register, the D-input of the first trigger and the first input of the AND-OR-NOT element are connected to the single output of the second trigger, the zero output of which is connected to the second input of the sixth AND-NOT element of the memory management unit, the first input of the IED element and the second input the element AND-OR-NOT is connected to the synchronous synchronization of the electronic computer, the second input of the element and the R-input of the second trigger are connected to the output of the confirmation of capture of the electronic computer, the C-input of the second trigger is connected to the output of the second element a AND, the first input of which is connected to the counter overflow code, and the second input is NOT connected to the switch output through the first element, the third trigger input C-input is connected to the third AND code of the third element, the first and second inputs of which and the second input of the first element

And connected to the control outputs of the busbar capture of a group of control buses of the electronic :: th computer, the R-input of the third trigger is connected to the output of the AND-OR-NOT element, the third input of which is NOT connected to the general reset of the device through the second element, the output of the first element And connected to the S-input of the fourth trigger, the C-input of which is connected to the zero output of the first trigger, which is connected to the lock input of the switch, the output of the third trigger is connected to the input of the bus seizure request of the electronic computer, the output A second trigger is connected to the first control input of the switch. The second, third, and fourth control inputs of which are connected respectively to the counter output, the write control output, and the control output of the memory adapter, the information inputs and outputs of the buffer memory are connected to the information inputs and outputs the electronic computer, the reset inputs of the counter, the mode register, the memory adapter are connected to the general reset bus of the device, the information and control inputs of the mode register are connected to the information onnoy and control buses electronic computer, inputs a write lock, starter and synchronization adapter memory are connected respectively to vkodom overflow counter tires acknowledgment Shin capture and synchronize electronic computer.

one

The invention relates to computing and can be used to verify the operability of the network and diagnose malfunctions of digital microcomputer modules.

The purpose of the invention is to reduce the equipment of the control device. ;

FIG. 1 shows a diagram of the device for the exchange of information between the object of control and the electronic computing machine (computer); Fig.2 is a block diagram of the installation of the control mode; in fig. 3 is a diagram of a memory management unit.

The device contains a buffer memory 1, a counter 2, a memory adapter 3,

bidirectional switch 4, the second group of inputs and outputs of which are connected to the corresponding information 5, address 6 and control electronic buses 7

machines, and the first group of 8 inputs and outputs - with the corresponding inputs and outputs of the control object, mode register 9, mode setting unit 10 control unit 11, memory management bus sampling bus 12, installation unit 13, prohibition bus 14, bus support 15 and 16 device processor and processor under test, bus 17 and 18 request for capturing the device processor bus and processor under test, lock bus 19, synchronization bus 20, overflow bus 21, interface bus 22, service bus 23, buffer memory management bus 24, control bus 25 sp Tui memory bus, the memory gate 26, bus 27, buffer memory address bus, the unit 28 increments the counter reset bus 29, control bus 30 capture. The control unit installation block diagram (Fig. 2) includes a blocking trigger 31, an auxiliary trigger 32, triggers 33 and 34 of a request for shutting down the processor of the computer and the processor under test, logic elements 2I-HE 35 and 36, 2I 37-39, 2-2I-OR -NE 40, inverter 41. The bus 13 of the installation in block 15 receives the contents of bits 42. and 43 of the mode register 9, which determine the program setting of the processor locking and turning off the processor, respectively, and the bus 30 of the control - signals Kom.ZP. WU 44, VK RR (selection of register 9 modes) 45 formed by a computer processor on control bus 7, signal VC (x) 46. (selection request latch 34 turning off the test processor) generated test processor and supplied from the switch 4 to the control pshnu; The memory management block diagram (Fig. 3) includes a decoder 47, invertors 48-53, elements ZI-NO 54 and 55, elements 2I-NO 56-62, element 4I-NO 63, element 2-2I-2, OR-NOT 64, Earth bus 65. The contents of bits 66, 6, and 68 of mode register 9, which determine the choice of the type of control information, are fed in via bus 13 of the sample. Acceptance signals (data outlays) 69, ACU BP (selection of buffer memory 70, Sample 71 (identifier of the command retrieval cycle), Service 72 (write to memory). Signals are received via service bus 23 FT 73 (writing to the buffer 84. Serial memory 1 during the monitoring of the memory modules) and MF + 1 74 (unit increment of the counter 2). The unit generates signals to control the buffer memory 1: Receiving the BP 75, CH.CFTPB 76 ( strobe memory selection) and the Issuance of the BP 77, - enters 1 bus on the bus 24. Consider the operation of the device on the example of its implementation on the basis of microprocessor About the K580 kit. The device implements: self-testing of modules containing a microprocessor by connecting the module under test to the system address and control data buses (i.e. the microprocessor under test can access the device’s memory to perform self-test programs); sequential recording of information circulating during testing on the data bus to the buffer memory in one of the modes of recording only commands, only data, command and data from test memory; Testing and processing of test results are separated in time, which allows testing at the operating frequency (at the same operating frequency of the entire device and the modules under test) and developing flexible diagnostic algorithms based on the processing of the operation protocols. The microcomputer module under test is connected to the input pins of the commutator 4. After powering on the device, the computer processor automatically resets the entire device via bus 29, and block 15 generates a bus 19 lock signal from switch 4 (Fig. 2), which ensures disconnection of the module under test system data bus 5, addresses 6 and control 7. The computer processor polls the control panel (not shown), where the operator dials the code of the module under test. Depending on the information received, the following modes of operation of a computer processor are possible. When the modules containing the microprocessor are monitored, the bus goes to the bus seizure state (i.e., the third state equivalent to disconnecting from the system buses 5, 6 and 7) the lock 19 of the switch 4 is reset and the test programs of the microprocessor are triggered. When the memory modules are monitored, the bus seizure reset locks the bus 19 and initiates the launch of the memory adapter 3, which forms the monitoring memory test while monitoring the interface modules and resetting the bus locking 19 and generating the control tests. The general control of the device modes provides the mode register 9, which is loaded by software over the data bus 5. The first group of 12 bits of the mode register 9 codes the modes of testing and processing protocols (diagnostics) and the type of information recorded in the buffer memory 1 (i.e. contents of the protocol), the second group of 13 bits is intended for software self-installation of the computer processor in the bus capture mode and resetting the bus lock of the switch 19 4. The process of monitoring and diagnostics requires multiple automatic switching of the computer processor and Nogo active state to a passive (capture ishn). Conversely, for the purpose of shaping and processing protocols in accordance with the control and diagnosis algorithms, the device includes a control mode setting unit 15 (Fig. 2), the main modes of operation of the latter are: setting the initial bus lock 19 when power is turned on device or system reset; withdrawal of the test module self-monitoring mode with a microprocessor; exit from the self-control mode by the VK (x) 46 signal (request of the microprocessor under test for disconnection by switching to the busbar capture state); exit from the self-monitoring mode by the overflow signal 21 of the counter 2 (buffer memory 1 overflow); software reset of bus 19 lock: In the first mode, the Reset signal 29 sets the reverse output of the lock 31 trigger to one, i.e. A signal is generated. Block 19 and the capture mode of the tires of the cyclotor processor being tested (single signal. Capture (x) 18 is formed on element 2I 39 and trigger 34), at the same time elements 41 and 40 of the set O on output trig1 8 Gera 33 fixing the absence of processor buses COMPUTER. Thus, the Reset signal blocks the switch 4, seizes the tires of the microprocessor under test, and enables the computer processor to work. In the second mode, the computer processor on the signal Kom.ZP.VU 44 (recording to an external device) loads into the mode register 14 a control word containing a unit in the bit corresponding to the request for the capture of tires of the processor of the computer and on the trailing edge of the sync pulse generated by the elements 2 and 37, according to the signals of Com.WHL.RTU 44 and VK RR 45, this unit, which enters block 15 via bus 13 (request signal 43), is loaded into trigger 33, and at its output, a single signal is generated. An encoder 17 enters into a computer processor. Upon transition to the execution of the next command, the computer processor analyzes the signal Zarsvat 17 and generates a signal Under 15, identifying the confirmation that captures its transition to the disabled state. Signal Confirmation of the grip 15 is gated on the element 2I-NO 35 clocks with a sync pulse 20, throwing the locking trigger 31 into an inverse state, i.e. the lock is reset (setting the signal of Lock 19 to one) and simultaneously resetting the tire capture of the microprocessor under test by writing to trigger 33 zero on the leading edge of the signal of Lock 19. Thus, in the second mode, the signals are generated: Capture 17 (one), Confirmation of capture 15 (unit), Lock 19 (unit), Capture (x) 18 (zero) ensure the transition to self-control. The third and fourth modes are used for normal and emergency exit from the self-monitoring mode. In the case of a working processor under test (third mode), the self-test program is executed, and the last command of the program is the command to load the capture request trigger 33. This command generates a zero signal VK (x) 46 received via bus 30, which sets the trigger 33 is in one state, i.e. Capture (x) 18 signal is generated. Capture signal (x) 18 through commutator 4 is fed to the processor under test which has accumulated a unit capacity Confirmation of capture (x) 16 identifying the tripping of the processor under test, on the positive front of which the trigger 32 is thrown into one unit, in the next clock cycle on the trailing edge of the signal 20, the blocking trigger 3t (setting the signal to Block 19 to zero) and the trigger 33 (setting the signal to Capture 17 to zero). In the event that the processor under test fails (fourth mode), it will perform a random set of functions instead of the self-test program, which represent a distorted interpretation of the self-test program. In the counting state, a non-corrupted processor can be indefinitely until a random stop command is executed. At the same time, the protocol of operations performed by the processor under test is framed in the buffer memory 1. The complete filling of the buffer memory 1 is identified by a pulse. Overflow 2 is generated by the counter 2. This pulse of negative polarity through the element 2 and 38 enters the synchronous input of the trigger 32 and transfers it to the unit. Further installation of the Signals 19 and 19 Capture 17 is carried out similarly to the third mode. In the fifth mode, the computer processor sends a control word to the mode register 9, containing a zero in the bit corresponding to the lock release, and on the falling edge of the indicated signal, into the mode register 9 via the bus 13 ( blocking reset signal 42), sets the inverse of the lock trigger 31 to one, i.e. produces a single signal Lock 19. The main purpose of the memory control block 11 (Fig. 3) is to generate control signals for the buffer memory T depending on the control mode specified by the first group of bits 66, 67 and 68 of mode 9 bus 12. For organizing a flexible monitoring and diagnostics process, memory management unit 11 implements: recording only commands (used to monitor the correctness of the execution of programs by the self-monitoring of the processor used); recording only data (used to control the correctness of command execution by the processor under test), sequential recording of commands and data (used for step-by-step monitoring of program execution, as well as in special diagnostic modes); data recording during memory testing (used when checking a memory card); reading the contents of the buffer memory (used when processing the test protocols of the tested modules). In the first four modes, the unit potential VC BP 68, which is fed through bus 22 to the input of inverter 58, holds the signal unit to unit, Receive BP 75, tunes the input drivers of the buffer memory 1 to receive information, and the ZP.ChTP signal. 76 repeats BP 77. In the first mode, the 111 combination (66.67.68), the zero potential at the output of the A3 decoder 47 sets the output of element 56 to one, while the unit potentials of the remaining outputs of the decoder 47 set the outputs of elements 55, 58 and 59 to one. In the first cycle, any computer processor generates a signal on the bus 22. In the second mode - a combination 001 - produces a zero potential at output B1 of the deptfrarator 47. Writing to the buffer memory 1 occurs either at the moment when the signal from the processor receives the signal 70 if signal Sample 71 is zero, or signal is signal 72. In the third mode — the combination 010 — produces a cool potential at output B2 of the decoder 47. Writing to buffer memory 1 takes place at the moment the computer receives signals 70 and Extras. and 72 is similar to the first and second modes. In the fourth mode, the combination 011-, the zero potential at the output of the OT of the decoder 47 is entered. The buffer memory 1 is stored at the moment when a single signal is received from the adapter 3 of the memory FL through the bus 23. In the fifth mode, the combination 100 none Out of the active outputs of the decoder 47 is not selected, and the signal Issue BP 77 is set to one. On command of the external device readout, the computer processor generates zero signals Receive 70 and VC PSUs 69, coming through inverters 48 and 49 to element 2I – NE 60, at the output of which zero signals are generated. At it, VP 7 and through element 2I 62 PLC. .BP 76 identifying readings from the buffer memory 1. In order to prevent distortion of the gt-protocol of the functioning of the module under test during an emergency exit from testing and for self-control of the entire device, a ban 14 signal generated by the unit 15 is used. The zero ban signal 14 entering the input of element 2IHE 61 establishes a signal. 77 into the unit, by the blocking block, recording into the buffer memory 1. The memory control unit 11 also produces a zero, increment signal 28 of the counter 2 on the element 64 in the multiplexed mode; either by the signal ZP.CHT.BP 76, or by the signal cottage FT 74. Thus, for each back (positive) edge of the signal of a single increment 28 (i.e., at the moment of the end of the next recording in the buffer memory 1) the contents of the counter 2 increases by one. The memory adapter 3 and the counter 2 are used to organize the monitoring of the memory modules at the operating frequency of the device. The memory adapter 3 provides the formation of control signals for the test memory according to the March test algorithm. At the same time, the contents of counter 2 are flushed to the memory under test via switch 4.

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Claims (1)

DEVICE FOR INFORMATION EXCHANGE BETWEEN CONTROL OBJECT AND. An electronic computer containing buffer memory, the address inputs of which are connected to the counter output, a bi-directional switch, the first group of information inputs and outputs of which is connected to the group of information inputs and outputs of the monitoring object, and the second group of information inputs and outputs with a group of information, address and control tires of an electronic computer, a memory adapter, characterized in that, in order to reduce equipment, the device comprises a control mode setting unit, a control unit memory, mode register, and the memory control unit contains a decoder, elements NOT, NOT, the first and second outputs of the decoder are connected to the first inputs of the first and second elements And, the second inputs of which are connected to the third output of the decoder, and the outputs to the first inputs respectively, of the third and fourth AND-NOT elements, the outputs of which are connected to the first and second inputs of the fifth AND-NOT element, the output of which is connected to the first input of the sixth AND-NOT element, the outputs of the first and second elements are NOT connected to the first and second inputs of the seventh AND-NOT element, the output of the second element is NOT connected to the second inputs of the third and fourth AND-NOT elements, the output of the third element is NOT connected to the third input of the fourth AND-NOT element, the output of the second AND-NOT element and the output of the fourth element are NOT connected to the first and the second inputs of the eighth AND-NOT element, the output of which is connected to the third input of the fifth AND-NOT element, the fourth input of which is connected to the output of the ninth AND-NOT element, inputs connected to the outputs of the fifth and sixth elements NOT, the outputs of the sixth and seventh elements AND N connected to the first and second inputs of the tenth AND-NOT element, the output of which is connected to the first input of the eleventh AND-NOT element, the second and third inputs of which are connected with • the output of the sixth element AND and the fourth output of the decoder, the inputs of which are connected to the outputs bits of the selection of the type of control information of the mode register, the inputs of the first, second, third and fourth elements are NOT connected respectively to the read and write outputs of the group of output control buses of the electronic computer, the outputs are six go, seventh and tenth elements AND are NOT connected respectively to the inputs of the record, SIJ ,,,, 1156078 reading and blocking the recording of buffer memory, the output of the sixth element is NOT connected to the gate input of the fifth element NOT and the fourth input of the eleventh element AND, the output of which is connected to the counter input of the counter, while the control mode setting unit contains four triggers , elements AND, AND-NOT, AND-OR-NOT, The S-input of the first trigger and the first input of the first AND element are connected to the bus of the general reset of the device, the C-input of the first trigger is connected to the output of the AND-NOT element, and its R-input and D-input of the third trigger are connected to the outputs of the discharges of the modes of blocking the mode register , D-input of the first trigger and the first input of the AND-OR-NOT element are connected to a single output of the second trigger, the zero output of which is connected to the second input of the sixth AND-NOT element of the memory control unit, the first input of the INE element and the second input of the AND-OR element NOT connected to sync bus cations of the electronic computer, the second input of the AND-NOT element and the R-input of the second trigger are connected to the bus capture confirmation output of the electronic computer, the C-input of the second trigger is connected to the output of the second AND element, the first input of which is connected to the counter overflow output, and the second the input through the first element is NOT connected to the output of the switch, the C-input of the third trigger is connected to the output of the third element And, the first and second inputs of which and the second input of the first element And connected to the control outputs of the bus capture of the control bus group of the electronic computer, the R-input of the third trigger is connected to the output of the AND-OR-NOT element, the third input of which through the second element is NOT connected to the general reset bus of the device, the output of the first AND element is connected to S - the input of the fourth trigger, the C-input of which is connected to the zero output of the first trigger, which is connected to the input of the switch lock, the output of the third trigger is connected to the input of the bus capture request of the electronic computer, the output of the four of that trigger is connected to the first control input of the switch., the second, third and fourth control inputs of which are connected respectively to the counter output, the write control output and the control output of the memory adapter, the information inputs and outputs of the buffer memory are connected to the information inputs and outputs of the electronic computer, inputs counter reset, mode register, memory adapter are connected to the device general reset bus, information and control inputs of the mode register are connected to the information and controlling: the buses of the electronic computer, the inputs for blocking the recording, start-up and synchronization of the memory adapter are connected respectively to the counter overflow output, buses for confirming the capture of buses and synchronization of the electronic computer.