SU553612A1 - Device for calculating elementary functions - Google Patents

Description

one

The invention relates to the field of computing and can be used for hardware calculating the square root and squaring a given argument in specialized computing devices and machines.

A device for calculating elementary functions is known, comprising two one-bit adders-subtractors, three shift registers, a memory block, a sign analysis unit, and a control unit 1.

The outputs of the two shift registers are connected to the first inputs of two one-digit adders-subtractors, the outputs of which are respectively connected to the inputs of these registers, the output of the block and these tees is connected to the second input of the first one-bit adder-subtractor. The second output of the first shift register is connected to the input of the sign analysis unit, the output of which is connected to the control input of the single-digit cyiMMaTOpa-subtractor.

Its disadvantage is the complexity and low accuracy of the calculation of elementary functions.

The closest technical solution to this proposal is a device for calculating elementary functions containing four shift registers, the outputs of three of which are connected to the first

the inputs of the corresponding one-bit adders-subtractors, the outputs of which are connected to the inputs of the corresponding shift registers, the second output of the first shift register is connected to the first input of the sign analysis unit, the outputs of which are connected to the control inputs of all four one-digit totalizers-subtractors, and the outputs of the control unit are connected

with the control inputs of the shift registers and the input of the memory unit, the first output of which is connected to the second input of the first one-bit adder-subtractor. The disadvantage of it is that in this

the device squaring operation can only be performed indirectly by multiplication, and it is necessary to rebuild the links between the blocks. Also in this device

actions are performed on binary-decimal codes, which determines the complexity of the device.

The aim of the invention is to extend the functionality of the device.

(calculation of square root or square) without restructuring. The latter improves reliability.

This goal is achieved by the fact that the second input of the second one-bit totalizer is connected to the first output

the memory unit, the second output of which is connected to the first input of the third one-bit adder-subtractor, the output of which is connected to the second input of the fourth one-bit adder-calculator, the second output of the third shift register is connected to the second input of the sign analysis unit, and the second output of the second shift register connected to the input of the fourth shift register, the output of which is connected to the second input of the third one-bit adder-subtractor.

The block diagram of the pre-molded device is shown in the drawing.

The device contains one-bit combiners-subtractors 1-4 of combining type, shifting registers 5-8, memory block 9, character analysis block 10 and control unit 11. The outputs of totalizers-1, 2 and 4 are connected to their first inputs through shift registers 5, 6 and 7 respectively. The first inputs of block 9 are connected to the second inputs of adders-subtractors 1 and 2, the second output of which is connected to the first input of adder-subtractor 3.

Block 9 is made in the form of a one-way memory device in such a way that two words (constants of the form) and 2-2 (, g) where / is an iteration are simultaneously recorded at the same address, and they are sampled at each clock (shift) pulse. . The unit of analysis of the sign 10 is made, for example, in the form of a trigger with logical elements. The control unit 11 comprises a clock pulse generator, a distributor, a counter and logic elements. The device input in the case of calculating the square root is the input of the shift of its register 7, and the output is the output of the shift register 6. In the case of calculating the square, the input of the device is the input of the shift of the register 5, and the output is the output of the shift register 7.

Such an embodiment of the device circuit allows the calculation of the square root and square of a given argument. The device works as follows.

When calculating the square root, the specified shift is entered in the third shift register 7 in the parallel code. The first, second, and fourth shift registers 5, 6, and 8 are set to zero states.

The calculation cycle consists of n-iterations, where n is the number of bits of the argument. Each iteration is performed sequentially. In the iterated iteration, cells consisting of adders-subtractors 1-4 and shift registers 5-8 operate in parallel. The block 10 is supplied with the value of the sign bit of the shift register 7. From the second output of the block 10, a control signal defining the subtraction mode is supplied to the adder-subtractor 4. The mode of operation of the remaining adders-subtractors 1, 2 and 3 is determined by the control signal from the first output of block 10.

With a positive sign, the content of the shift register 7 in subtractor 1 is subtracted, and in subtractors of subtractors 2 and 3 is added, with a negative one - addition and subtraction, respectively.

In each iteration, algebraic addition of the next constant of the form 2 - (+ 1) with the previous content of the shift register 6 is performed in the adder-subtractor 2. In the adder-subtractor 3, the algebraic addition of the shifted register 6 with the next constant of the type 2- (- + i). In subtractor 4, the subtraction of the result obtained in the subtractor 3 is made from the content of the shift register 7. The results of the iteration from the outputs of the subtractors 1, 2 and 4 are minimized

they are written to older shear-discharged bits of shift registers 5, 6, and 7, and advance clock-shift (shift) pulses to the beginning of shift registers 5-7. Corresponding

The number of clock pulses to advance information in shift registers 5-8 is supplied from the outputs of control unit 11. After performing n iterations in shift register 6, the square root value is found.

In calculating the square, the given argument is fed in parallel code to shift register 5. The shift registers 6-8 are set to the zero state.

The block 10 is supplied with the value of the sign bit of the shift register 5. From the second output of the block 10 to the cz-mmator-subtractor 5, a control signal is applied that determines. work rest

totalizers 1-3 remains the same. The rest of the process of calculating the square is completely similar to the above. After performing n iterations in shift register 7, the value of the square argument is found.

The time for calculating the square root or square is equal to the cycles T (m – m, where m is the number of additional bits for computational errors in shear.

The presence of connections between the second input of the second one-bit adder-subtractor and the first input of the memory unit, the second output of which is connected to the first input of the third one-bit adder.-Subtractor, output

which is connected to the second input of the fourth one-digit adder of the subtractor, and the second output of the third shift register with the second input of the sign analysis unit, as well as the second output of the second shift register with the input of the fourth shift register, the output of which is connected to the second input of the third one-digit adder of the subtractor allows expand the functionality of the device, i.e.

calculate square root and squaring functions without restructuring.

Claims (2)

1. King V. Ya., Oransky A. M., Reichenberg A. L. High-speed interactional methods for calculating the square root. “Theory and application of mathematical tools, Minsk, ed. BSU them. V. I. Lenin, 1972, pp. 162-163. 2.Patent UK No. 1 321 067, G 4A, publ. in 1973.