SU532077A1 - Device for automatic assignment of time scales by radio signals - Google Patents

Description

time 2, in which the phase of the high-frequency filling of radio signals is remembered, carried out on work ethane, prior reception of amplitude-modulated (AM) time signals. The output of the storage unit 2 is connected to one input of the block 3 of the primary signal processing, the other input is iKOTOiporo (connected to the output of the radio receiver 4. The other output of the storage unit 2 is connected to the input of the controlled frequency divider 5. The output of the latter is connected to the input of the time counter 6, which determines the duration the time stamping process and the output connected to the polling counter 7. The inputs of the switch 8 channels are connected to the outputs of the polling counter 7 and the controlled divider 5. Each output 9 of the switch 8 canalV is equipped with inverters and two circuits and code units (for simplicity in Fig. 1, the nocables are inverters 10 and first 11 and second 12 combining units of the first channel code). The latter contain successively connected adders 13, 14 channels of delay nodes 15, 1-6 and OR circuits 17, 18, The inputs of which are connected to the CMPs of the coincidence 19, 20 for the first and second devices, respectively. The outputs 9 of the channel switch are connected to the summing inputs and reversible drive counters 21 through the first unified-ITIC combining schemes, and through inverters and second combining units of the code units to the subtraction conductive inputs corresponding counter-nakoniteley.

The outputs 9 of the second, third and fourth channels of the switch 8 are connected to the adder 13 and the inverters 10 to the adder 14 channels, and the output 9 of the first channel is connected to the coincidence circuit 19 directly, and to the coincidence circuit 20 via the inverter 10 The output of the OR circuit of the first COD // unit combination is connected to the summing input of the drive 21, the output of the OR circuit 18 to its subtractive input. The outputs of the drive counters 21 are connected to a logic circuit 22, the outputs of which are connected to a command unit 23, controlling the operation of the device and connected to the counters 6 and polling 7, and with a controllable frequency divider 5. The output of block 3 is connected to the inputs of the coincidence circuits 19, 20. The counting block 24 is connected to the time keeper 2 and the controlled divider 5 and is started by pulses of the latter, the limit is the rasog; Accuracy of the device time scales and exact time.

The operation of the device is carried out in the following manner.

Block 5 receives the voltage of the time signal with noise (Fig. 2a), separated by radio 4, and the reference gates from time store 2, combined in phase with high-frequency filling of the signal, for example, from the moment of transition through

zero signal. In the absence of a signal from noise exposure, signal units are also formed which are considered false. Their average number taken for a certain

a single period of time, for example, a repetition period of radio pulses, is less than the average number of code units carrying useful information for the same period of time. This is because the phase

Noise is random, and the phase of signal and noise is regular, p. However, this difference with a small signal-to-noise ratio is small. Units of code that carry both useful and false information.

the condominium schemes P9, 20 and the adders of the channels 13, 14 of the schemes for uniting code units (Fig. 26).

| With the help of a controlled frequency divider 5, a reference time scale is generated, which is tied to the radio signals of the exact time. The pulses of the controlled divider 5 arrive at the switch of 8 channels, by means of assistance (of which, at the outputs 9 of the switch of the channel, pulses are formed (Fig.

2c, g, d, e), equal to the duration of radio pulses of time. The temporal position of these pulses corresponds to accumulation channels, one of which contains the desired signal. The number of channels can be any

 Determined by the required binding accuracy. If the code units were directly distributed through the accumulation channels, then the difference between the number of them in the sigpal channel (Fig. 2c) and other channels, for example (Fig. 2d), would be small, since the code units corresponding to the signal mixture with noise and carrying useful information would fall into these channels and would be false with respect to the signal channel. For

The case shown in FIG. 2, the difference between the code units of the first (Fig. 28) and the second (Fig. 2d) channels during the radio pulse repetition period would be one pulse. In the device, with the help of the coincidence circuit 19, code units are formed that coincide with the impulse of the given output of the switch of 8 channels. For the first output 9, the commutator channels are units of code (Fig. 2g), coinciding with a pulse (Fig. 2c). With the help of the adder of channels 13 of the first scheme L of combining units of code, code units (Fig. 2h, s) are formed at its outputs, which fall into time intervals that correspond to the coincidence of the pulse given

channel with pulses of other channels. For the first output, the 9 switch of channels is the time intervals corresponding to the coincidence of n. Pulse (Fig. 28), alternately with pulses (fng. 2d, f). With the help of delay nodes 16, the set of code units of the merged channels is delayed relative to the code units at the output (Fig. 2g) of the circuit, we match 19, and the output of the ILR1 circuit 17 are formed and the ichrod (Fig. 2k) are directly present during the pulse and the pulse of the accumulation channel in other channels. These pulses are fed to the summing input of the accumulator counter. Using the second coincidence circuit 20, the code units (Fig. 2L) are formed, which coincide with the inverted output pulse of the switch, and the adder channels 14 of the second scheme 12, combining the code units of the form | Generates, on its outputs, code units (Fig. 2m, n) falling into coincident time intervals of inverted pulses (in other channels with inverted pulses of a given output. Combined by the OR 18 scheme of the second unification scheme 12, a set of code units from the output of the channel 14, contained in other channels of the code, from the output of the circuit Adeni 20 is fed to the subtracting input of the counter-accumulator (Fig. 2 "). At the output 9 of the channel corresponding to the time radio signal, the summing input of the counter-accumulator 21 receives code units that carry useful information about the signal contained in all accumulation channels, and on the subtracting input, code units formed by the action of schum, thereby increasing the amount of information in the channel by using code units carrying useful information in other channels. At the output 9 of the accumulation channel, which does not correspond to the signal, for example, p of the second channel, the summing input of the drive counter 21 comes in code units corresponding to the parts of the signal and sound contained in all channels during the pulse (Fig. 2d) This channel, on the subtracting input - code units from the coincidence of the remaining part of the signal and noise, since the inverted channel impulse lends a part of the signal that does not overlap the pulse of channel 9. At the same time, part one (code that carries useful information but is false foranal and recorded on a summing input of the counter, is compensated for code units carrying useful information and recorded by subtracting input drives the counter.

In the time determined by the time counter 6, a significantly larger number of code units will accumulate in the storage counter corresponding to the signal frame, than in other storage counters. The output impulse of the time counter 6 turns on the polling counter 7, which is used to refill the drive counters 21, and first with high confidence fill the channel counter to which the signal corresponds. Using the logic circuit 22, combining the outputs of the drive accumulators 21, the channel number is set to which the filled counter drive 21 corresponds, and the output from the logic circuit 22 goes to the command unit 23, which sets the scale of the controlled frequency divider

About a received radio signal of time and a switching device as a whole for the next cycle of operation, i.e., a reference scale to radio signals of a lower tracking frequency. At the same time, the necessary capacities of the time counters 6 and of the interrogation 7 and the frequency of the pulses of the controlled divider 5, which synchronizes the channel switch 5, are set.

When the device operates on radio signals of time with low noise level, when the probability of correct detection of the signal -hmgt increases, the device can be supplemented, if necessary, with a simple control circuit, which should produce an adaptive reduction in the time of the binding process (depending on the signal-to-signal ratio). noise) by changing the capacitance

time counter or drive counters.

Claims (2)

1. A device for automatic assignment of time signals by radio signals of exact time, containing a reference generator connected through a time keeper to a primary signal processing unit, another input of which is connected to the output of a radio receiver, ks.mutator channels, 1 counters of memory connected to command block, controlled divisor h, asthoty, connected to the time keeper, to the channel switch and to connected time and polling counters, and reference unit connected to the control A divider and a time keeper, the output of the command unit is connected to a controlled frequency divider, a time counter and a polling counter, the output of which is connected to a channel switch, characterized in that, in order to ensure reliable binding, each output of the channel switch it is equipped with inverters and two schemes for uniting code units, all the outputs of the channel switch are connected through the first of all the units of code to the summing inputs of the corresponding drive counters, and through the connected In practice, the inverters and the second combination circuit of the code units are to the subtracting inputs of the drive counters. 2. A device according to claim 1, characterized in that each unit combining unit of code is implemented as a series-connected adder of channels, delay nodes, and OR circuit. and a matching circuit is connected to the input of the latter. Sources of information taken into consideration.: Anig in the examination of the application. 1. Auth. swith jVo 443360, .M .. Cl. G 04 C 11/02. 1974. fui.l I I I iLJ,; L t-JL i J i