SU530467A1 - 2.5 frequency divider - Google Patents

Description

one

The invention relates to automation and computing and can be used in devices where frequency division by a multiple of 2.5 is necessary.

Known frequency division device

2.5, containing potential triggers on the I-HB elements and series-connected elements of NAND, to the inputs of each of which the input bus is connected, and the outputs are connected to the single inputs of the trigger.

However, such a device is implemented on significant equipment.

The closest in technical essence to the present invention is a device comprising triggers on AND-NOT elements of an inverter and AND-NOT elements, wherein the inputs of the first AND-NE element are connected to the single output of the first trigger and the output of the second AND-NE element, zero and single outputs The second trigger is connected to the first inputs of the third and fourth elements of the NAND, respectively; the zero outputs of the third, fourth, and fifth triggers are connected to the zero inputs of the fourth, fifth, and third triggers, respectively; the output of the second IS-NOT is connected to single inputs of the third and fifth triggers and to the first input of the fifth NAND element, whose output is connected to the single inputs of the fourth and fifth triggers and to the first input of the sixth NAND element, whose output is connected to single the inputs of the third and fourth triggers and to the first input of the second element NAND.

However, this device is also implemented on significant equipment, which reduces the reliability of its work.

The purpose of the invention is to increase the reliability of the divider.

This is achieved by the fact that in the proposed divider, the second inputs of the second, fifth and sixth elements AND-NOT and the input of the inverter are connected to the input bus, and the single input of the first trigger is connected to the output of the inverter and the output of the third element IS-NOT, zero input with zero the third trigger and the single output with the second input of the third NAND element, with zero and single inputs of the second and fifth triggers, respectively, while the output of the second AND element is not connected to the single input of the second trigger and the second input about the NAND element, the code of which is connected to the third input of the second NAND element. FIG. Figure 1 shows the structural electrical circuit of the proposed frequency divider by 2.5; Fig 2 is a temporary diagram of his work. The divider contains 5 potential triggers on the elements AND-NOT 1-10, the elements AND-NOT 11-16, the inverter 17, the input bus 18. In the initial state, the fifth trigger is in the unit, and the remaining triggers are in zero. The signals at the outputs of the remaining elements correspond to the signals shown in the temporal diagram (Fig. 2). The divider works the trace in a skinny way. When the first impulse arrives at the input bus 18, an AND-NO 15 element will work, which will write a unit into quarters trigger, and the output connection of the IS-NOT element 15 to the input of the IS-NOT element 16 will prohibit the response of the IS-16 element during the first pulse, The connection of the zero output of the fourth trigger with the zero input of the fifth allows the fifth trigger to set the fifth trigger to zero during the first pulse at the output of the unit arm of the fifth trigger logical unit, as it is supported by the output connection of the AND-15 element. in the input element AND-NOT 10. The values of the outputs of the remaining elements during the action of the first pulse are shown in the time diagram (Fig. 2). Similarly, when the second pulse arrives, the AND-HEY element 16 is triggered, and the unit is rewritten into the third three ger, and as soon as the third pulse arrives, the unit is rewritten into the fifth trigger (element 12 is triggered). During the third pulse, the output of the circuit logical unit, the duration of which coincides with the input signal. The input signal forms the element AND-NOT 16, since its input receives a logical impulse O from the output of the element IS-NOT 12. The signal from the output of the element IS-NOT 12 also enters the single input of the second trigger and sets it to one, the second trigger of the control And through the elements AND-NOT 13 and 14 elements .mi AND-NOT 2 and 12, which form the desired frequency at the output of the circuit. Items

Claims (1)

NAND 2 and 12 are triggered alternately, when the third trigger is in the state of one, and the second trigger sets the sequence for triggering these elements. The AND-NE 12 element generates an input signal during the pulses at the circuit input (provided that the third trigger is one, and the second is at zero), and the AND-NOT 2 element - during the pause between the pulses at the circuit input ( provided that the third and second triggers in the unit). From the output of the inverter 17, the inverted input signal is fed to the input element AND IS NOT 2, allowing the latter to operate during the pause between pulses at the input of the circuit. The .AND-NOT element (zero shoulder of the first trigger) permits the input state of the third trigger to be recorded at the input of the AND-NOT element 2 and does not respond to the transition of this trigger to zero while the AND-NOT element forms the output signal. This is assisted by the connection of the output of the zero arm of the third trigger with the zero input of the first trigger, which is confirmed by the timing diagram of the device circuit., Invention Divide frequency 2.5, containing the triggers on the AND-N elements, the inverter and the N-elements, and the inputs the first element of the first trigger is connected to the single output of the first trigger, and the zero and single outputs of the second trigger are connected to the first inputs of the third and fourth elements of the third and fourth elements, respectively, of the third and fourth the right and fifth triggers are connected to zero inputs of the fourth, fifth, and third triggers, respectively; the output of the second NAND element is connected to the single inputs of the third and fifth triggers and to the first input of the fifth NAND element, the output of which is connected to single inputs the fourth and fifth triggers and with the first input of the sixth element NAND, the output of which is connected to the single inputs of the third and fourth triggers and to the first input of the second element, characterized in that, in order to increase the reliability of the device, The second inputs of the second, fifth and sixth elements AND-NOT and the input of the inverter are connected to the input bus, the single input of the first trigger connected to the output of the inverter and to the output of the third AND-NOT element, the zero input with the zero input of the third trigger, and the single output - with the second input of the third element IS-NOT, with zero and single inputs, respectively, of the second and fifth triggers, the output of the second element AND-NOT connected to the single input of the second trigger and the second input of the fourth element AND-NOT whose output is connected to the thirdthe input of the second element is NOT. bTLTLrUb i-he 5 and-he 6 and-not 7 FIG. 2 Lj u