SU530438A1 - Infra-low frequency digital generator - Google Patents

Description

one

The invention relates to digital computing technology and can be used as a control clock generator in automatic control devices,

A pulse generator is known comprising a clock pulse generator, a counter, a frequency divider, an output trigger, and a comparison circuit code ij.

However, such a generator does not allow

receive sinusoidal voltage.

Of all the known devices, a voltage generator approaching a sinusoidal, which contains a clock pulse generator (GTI) connected to the input of a reversible counter, the older bit of which is connected to the control input of the switch, is the closest to the invention in its technical essence. The other three outputs are connected to the control inputs of the first controlled voltage divider, the threshold input of which is connected to the reference voltage source. The second input of the second voltage divider is connected to the output of the first control voltage divider, the control inputs of the latter are connected to the inverted outputs of the counter, and the output to the main input of the polarity switch 2.

A half wave of sinusoidal voltage is approximated by a parabola formed by the simultaneous antiphase operation of two voltage dividers: the linearly increasing voltage of the first is divided by the second linearly decreasing law.

The amplitudes of the harmonic components decrease in proportion to the cube of the number of harmonics. Taking into account the third and fifth harmonics, the harmonic coefficient is 4.5%, which is unacceptable in a number of cases.

In the known device, cascade connection of code-voltage converters is used, which complicates the circuit and doubles the error of the device.

The purpose of the invention is to reduce the harmonic ratio of the output voltage.

This goal is achieved due to the fact that a digital infra-low frequency generator, containing a clock pulse generator, a reversible counter, a controlled voltage divider, whose threshold input is connected to a source of reference voltage, and an output to the input of a field switch , a trigger is introduced, the counting input of which is connected to the output of the clock pulse generator, the first and second switches and four decoder, the outputs of which are connected to the outputs of the reversible counter, the OR element whose output is connected to the control input of the reversing counter, one signal input of the first switch is connected to the trigger output, another signal input is connected to the output of the clock generator, the control input is connected to the output of the second decoder, and the output is connected to the counting input of the reversible counter, the outputs of the first and fourth decoders connected to the inputs of the OR element, the input of the third decoder is connected to the control input of the second switch, the signal inputs of which are connected to the output of the reversible counter, and the outputs Keys to the inputs of a controllable divider, upraBl yush.y input polarity switch connected to the output of the first decoder.

FIG. 1 shows the structural electrical circuit of the device; in fig. 2 - approximation of the half-wave of a sinusoid by a parabola; on fyu. 3 - piecewise linear approximation of the half-wave of a sinusoid.

The infra-low frequency digital oscillator consists of 1 clock pulse generator (GTI), trigger 2 with a counting input, first switch 3, reversible counter 4, second switch 5, controlled divider 6, Tpach switch, 8-11 decoders, element 12. FIG. 2 and 3, reference numeral 13 denotes a half-wave of sinusoidal oscillation,

14 - approximation of a sinusoid by a parabola

15 is a piecewise linear approximation of a sinsoid, 16-17 are points corresponding to the response times of the first decoder 8, 18-19 points corresponding to the response times of the second decoder

9, 20-21 points corresponding to the operation times of the third decoder 10 22 —the point corresponding to the operation time of the fourth decoder 11.

For proper operation of the device, it is necessary that the control inputs of switches 3 and 5, counter 4 and polarity switch 7 be countable, i.e., that when the first control pulse arrives, they go into a new state, with uocT power of the second pulse - into the former state and etc.

Before operation, the device is in the initial state: counter 4 is in the zero state. The signal from the output of the GTI 1 through the commentator 3 goes directly to the input of counter 4, operating in the direct counting mode. Switch 5 provides a signal from the output of counter 4 to the inputs of a controlled divider 6. Polarity switch 7 operates in positive polarity mode. After the start signal, the counter 4 starts and accumulates the e.ainiHiibJ, as a result of which the linear output of the continuous voltage is generated at the output of the device. The slope onstage voltage is determined by the frequency of the repetition of the pulses of GTI 1 and the magnitude of the discreteness of the controlled divider G,

At the moment of accumulation of the scsi-aco 4 stroke of the corresponding memory of the freezer 9 (button 17 in fig. 3), the commutator under the control switch from the output of the decoder 9 switches, and the pulses from the output of the relay are started at the input of the slider; - Ore 2, the repetition rate of cohorts x is half the initial one. The steepness of BbixoaHoro agrastania, for example, is also twice as vrioiib.

At the moment of accumulation in the counter 4. Demo coagvex; code decoder 10 (point 2O in Fig. 3), switch 5 supplies the inputs of the controlled divider 6 with the dead code corresponding to the code of the descrambler 10. As a result, living

At the moment of accumulation of the decoder 11 corresponding to the code in the counter, the element OR 12 turns on the counter of the counter 4. The code in counter 4 begins to decrease, and the process proceeds in the opposite direction,

At the moment that 4 is set in the counter, the corresponding decoder code & (point 17 in Fig. 3), the OR circuit 12 again switches the reverse of the counter 4 and the polarity switch 7, the cycle repeats but the output voltage of the device is: the effects have already negative polarity, t, i.e. a negative noayBOJiaa output voltage is generated wives

Such a digital generator-ore will provide a coefficient of the harmonic coefficient K., 1.7 ,. This is 2j5 times less compared with the known devices.

Claims (2)

Invention Formula An infra-low frequency digital generator containing a clock pulse generator, a reversible counter and a controlled voltage divider, the threshold input of which is connected to the reference voltage source, and the output to the input of a polarity switch, in order to reduce the harmonics of the output voltage trigger, the counting input of which is connected to the output of the clock pulse generator, the first and second switches and four decoders, the inputs of which are connected to the outputs of the reversible counter , the OR element, the output of which is connected to the control input of the reversible counter, one signal input of the first switch is connected to the trigger output, another signal 20 1/00, 07/14/71. the input is connected to the clock pulse output, the control input is connected to the output of the second decoder, and the output is connected to the counting input of the reversing counter, the outputs of the first and fourth decoders are connected to the inputs of the OR element, the input of the third decoder is connected to the control input of the second switch, signal the inputs of which are connected to the output of the reversible counter, and the outputs are connected to the inputs of the controlled divider, the control input of the polarity switch is connected to the output of the first decoder. Sources of information taken into account in the examination; I.ABT. St. No. 420093, cl. N OZ K 1/18, 03.20.72 (equivalent) 2. Auth. St. No. 388348, cl. H 03 K 6th Stage direction FIG. f Angle sRig.Z