SU525095A1 - Device for controlling communication channels of a computer system - Google Patents

Description

the third control output of the device,: the third inputs of the interrupt block KponporpaMMiiOro and the channel address setting block, the fourth control input of the information switch and the first input of the analysis block, the state of the second, third and fourth channels of the channel state analysis and selection The channel operation modes are connected respectively with the second, third and first control inputs of the device, the output of the channel state analysis block is connected to the fourth input of the microprogram interrupt block and the fourth control to the output ode device.

The selector channels connected to the device for controlling the channels have the same structure and are controlled by the firmware common to both channels. This allows the simplified program to organize work with an external device.

a selector channel using a serviceable selector channel, while it is not busy working with its external interface. The channel operation mode selector unit transfers the faulty channel to the mode of finding and localizing the malfunction. The signals generated in this case, in the channel operation mode selection block, block the signal output circuits of the faulty channel. As a result, a faulty channel can only receive information from the device for controlling the channels and the external device. The equipment of both channels works synchronously, since it is exposed to the same effects as from the device for controlling the channels and from the side of the external device. Using the state analysis block, the channel, the reactions of both channels are compared and the processor is informed about the state of the hardware of the failed channel at the moment bo, FIG. 1 shows a block diagram of the proposed device and its connection with other devices of the computing system; in fig. 2 diagram of the channel operation mode selection block; in fig. 3 is a block diagram of a channel status analysis. The channel control device 1 shown in FIG. 1 is intended for connecting to the processor 2 of the first and second cord of selector channels 3 and 4, respectively, and a multiplex channel 5, and controlling the transmission of pilot information and data between the channels and the processor. The processor 2 controls the operation of the system as a whole, performs the functions of storing, processing and organizing the transfer of information. The system control panel 6 is designed to manually control the operation of the system,

Visualization: ontrol. and check, -, cheap preventive work.,

The selector channels 3 and 4 are intended for connecting external devices, containing the necessary registers for storing the control information, which is created for organizing and maintaining input and output.

External devices 9 and 1O are connected to selector channels 3 and 4 through the BOM of the I / O interface 7 and the interface switch 8, respectively.

The device 1 comprises a firmware interrupt block 11 a channel address setting block 12, an information switch 13, a channel operation mode selection block 14 and a channel state analysis block 15.

The exchange of information between external devices 9 and 10 and processor 2 is em

which uses the device 1 to control the channels. Information is exchanged via commands from the processor, in which the channel number and the internal & external device are indicated. The I / O command code, the head address of the memory, the counter of data bytes transmitted by this command, and other control information are output by the processor through special control signals.

30 words. The received channel word is formed from the received information, which contains the information necessary for the input and output operation, and stores it in its registers / or in special areas in one of the main system functions in the processor. The transmission of control information between the processor 2 and the channel registers is carried out through the system of output information buses 16 and the control buses of the processor 17. The sign of the channel, to the registers of which the control information is transmitted, is generated by block 12 And through the buses 18, the signs of the channel are sent to the channels. The contents of the channel registers can be firmware. analyzed through the output information buses I 19 channels, bus 2 O channel conditions, through the elements AND 21, 22 (23, 24), OR 25- (2.6) information switch 13 and the system of input information and control buses 27 of the processor. : When it detects a failure in the equipment ka-. A malfunctioning channel is excluded from the work and is translated into a search and localization mode. Need exclude. A channel from the operating mode can be determined by the operator or the utgravl program (by the supervisor) and communicated through the output (console) device. (Iterator, having been instructed to switch i1npg)

the channel is in the mode of blocking the fault malfunction, setting up on the control panel 6 control unit, the exclusion mode of the malfunctioning channel, and through the control bash 28 a signal is output that goes to block 14 to select the channel operation mode. The signal of one of the channels and synapses from the console 6 / - / board in the channel operation mode selection block 14 generates a blocking signal that, through the locking and control pins 29 and the control panel, enters the switch i 13 information: page 1. switch 8 interfaces. This Signal is blocking; issuing 1 information from the faulty channel, / After that, the processing system can continue its work. When the current program encounters a command to access external device 9 (s), the processor 2 analyzes the channel status before its execution and, if channel 20 is faulty, corrects the channel address in key 12 to set the channel address (replaces it with of the healthy channel, but in the ffi program performed by the channel address 38 is changed), after which the unit 14 of the selection of the channel’s mode 25 produces an interface switching signal (if the healthy channel is idle), incoming busbar busbar 29 and switching control. This signal in the switch 8 of the interface 30 is provided by connecting an external device: a right channel to the healthy channel, and an r.aiacra connection of the channel state analysis unit 15 to the channel state buses 20. At the same time, in channel selection mode block 14, a signal is generated that, through the locking and control buses 29; This signal in block 12 generates a enable signal for receiving information 40 into the registers of the faulty channel. Allowing the information to be entered into the healthy channel is accomplished by a signal of the channel operation signal issued by the block 12 | Through the bus signs 1S. Processor 45 2, loading the control information B, the registers of the healthy channel, loads

W 5E§M2 112 1 5-L 1:11 P55 y channel. After loading1 and control information into the channel registers, both channels perform one and 50 th input Output operation; the control & control function with an external device 9 (o) of a non-correct & t channel is performed by a healthy channel. The return signals from the external device 9 (o) through the bus of the interface 7 and the commutator - 55 mountains 8 interfaces come into both select channels 3 and 4. Thus, the equipment of the rims of the channels works synchronously, as it is subjected to OTDacac effects like

Claims (1)

, from the side of the device 1 for controlling the channels, as well as from the side of the external device 9 (o). The progress of the I / O operation in the faulty channel is analyzed using the channel state analysis and shutdown unit 15. Through the busses 20 channel conditions into the channel analysis unit 15, the same type of signals are output and compared. If the execution of the I / O operation is not associated with a faulty section of the hardware circuit, then the compared signals, characterized by the channel conditions, are the same for both channels. But as soon as you complete the I / O operation using the i; the faulty piece of hardware on the checked channel, this unambiguity is broken. In the channel state analysis block 15, a signal of state noncomparison and an interlock signal for the operation of an off-channel channel (i.e. synchronization circuits) are generated, which through the interrupt and stop buses 30 arrive at the microprogram 11 many interrupts and in the faulty selector channel 3 (4). The signal of state of incomparison in the microprogram interrupt block is generated and sent via interrupt bus 31 to processor 2 an interrupt request, during which the execution of the current sequence of microcommands is suspended and the control is transmitted to the serving microprogram, which records the state of the healthy channel registers in the diagnostic region processor memory as a reference. The signal for blocking the operation of the equipment of an inoperative channel in the channel records the state of the equipment in which it was at the time of the Fault detection. After writing the state of the registers to the diagnostic memory area of the processor, the servicing firmware transfers control of the current (paused) program and the input-output operation continues to run in a healthy channel. After performing the I / O days, the channel informs the processor 2 about the termination of work by setting up an I / O interrupt request; when this is done, the address of the malfunctioning channel is formed, the cake of the cause of the interruption. Control is transferred to the service of the firmware. From the processor 2, through the output control buses, 17 of the processor, a control signal is output to the channel mode selection unit 14, on which the blocking signal is taken. This allows the servicing microprogramme through the information switch 13 and the system of each information and control buses 27 of the processor to record the state of the registers and control of the points of the key channel in the processor's memory. After registering with registers, processor 2 issues a Reset | signal, through which the faulty 1 channel goes to its initial state. Both the selector channels after the I / O operations have been completed are in the same state as they were before the execution of the external device call command and are ready for K; the repetition of the process p of the diagnostic area of the memory of the memory is found (| jurmatization of the hardware condition (reference) and the malfunctioning channel at the moment of failure. The diagnostic region is analyzed by the control program by comparing the state of the analogous parts of the hardware and as a result of the analysis processor 2, through multiplex channel 5, provides the necessary information to the operator, which eliminates the fault and sets the channel operating mode by switching on the system control panel 6. An example implementation The mode selection unit 14 may serve as a block, shown in Fig. 2, which contains the first flush trigger 32, the second flush trigger 33, And 34, 35 sets of the first and second flip-flop triggers, respectively, trigger 36 (localization), switching trigger 37, elements And 38-41, NOT 42, 43, OR 44, And 45, Triggers 32, 33-bs are set through AND 34, 35 elements, if trigger (36) of the mode (localization) trigger is not set by the signal from the control circuit. processor 2, which arrives through the processor output control edges 17. The trigger 36 of the mode (localization) is set up from the control panel of the control bus 28 in setting the faulty channel to the localization mode. If a fault occurs from the channel, a trigger 32 (33) fails. A triggered trigger 32 (DZ) fails and a mode (localization) trigger 36 through an AND 38 element (39), an HE 42 element (43) and a lock switch and switching control are given a blocking signal, which enters the information switch and the interface mutator locks the elements And 20, 23 (21, 24). A trigger 37. switching is established through the output ports of the processor bus 17, element 45, processor 2 before starting an I / O operation, if the mode trigger 36 is set. Using the set switching trigger 37 and trigger 34 (35) failure, the MeJfT AND 40 (4l) plots / abuts the switching signal of the interface, which through the lockout and wired lines to (switch to the switch) it ”. According to this signal, the external device of the faulty channel is pushed to the healthy channel. Through the element OR 44, this signal enters the channel analysis unit 15 for connecting it to the 2 O channel state buses. The channel condition analysis block is shown in FIG. 3. It contains epemeitis. Comparisons AND 46-51, items NOT 52-57, OR 58, AND 59, 6O and the stop triggers of the first and second channels, respectively. The signals from the channels through the state bus 2O are compared in pairs on AND 46-51 elements. By comparing the signal of one of the pairs at the output of the element OR 58, a non-comparison signal is generated, which, via the interrupt and stop busses 30, enters microprogram interrupt block 11 to set the interrupt request. Elements And 59, 60 ut1ravl from the installation of the trashterov 61 and 62 stop, respectively. The corresponding stop trigger 61 (62) is established by a signal of incomparability to the trigger 32 (33) failure. The signal for blocking the operation of the equipment of the faulty channel (synchronization circuits) from the single arm of the flip-flop 61 (b2) of the stop is outputted through a series of interruptions and stops to the corresponding malfunctioning channel. Upon the completion of the input-output operation and transmission of control to the control firmware by the healthy channel, processor 2 generates a signal on which the trigger 32 (DZ) fails and the switching trigger 37 is reset (Fig. 2). Through the elements of AND 38 (GE) and 40 (4l), the blocking and switching signals are removed. Through the information switch 13 and the processor input information system 27, the latter removes the state of the faulty channel registers. After recording the information about the state of the hardware of channel 5, processor 2, via output control clamps 17, you give a reset signal, on which it drops. with the trigger 60 (b1) stop, and the equipment of the faulty channel goes back to its initial state. Thus, the device for controlling the channels allows you to organize the search and localization of the fault in one of the selector channels during the operation of the second (healthy) selector channel, which increases the useful system operation time by an amount equal to the time spent on the search and localization of neutrality when using well-known tools to manage channels in processing systems. Increase system uptime I | processing, in failure mode, decides the scope of its application for tasks (requiring continuity of information processing, Invention formula) A device for controlling communication channels of a computing system containing a microprogram interrupt unit, an information switch and a channel address setting unit; the first and second inputs of which are connected respectively with the first information and control inputs of the device, and the output is connected to the first control output of the device and the first control input / information switch, the first and the second Other information inputs and outputs are connected respectively to the second and third information inputs, the first and second information outputs of the device, the second and third control inputs of the information switchboard, and the first and second inputs of the microprogram interrupt unit are connected respectively to the second and third control receivers the device, the output of the firmware interrupt block is connected to the second control output of the device, from. In order to increase the production of the search operation and locate faults, a channel state analysis block is inserted into the channel mode selection block, the first input of which is connected to the fourth control input of the device, the output to the third control the output output of the device, the third inputs of the microprogram interrupt unit and the channel address setting unit, with the fourth control input of the information switch and with the first input of the channel state analysis unit, the second, third and fourth inputs of the blocks a Aleesa channel condition and channel mode selector are connected respectively to the second, the third and the first control input device, the output of the analysis block channel state is connected to the fourth input of the microprogram interruption and fourth controlled $ 5eyuschemu output device. 29 W .-,  T -: - - R l i-tlj j chg r Sh 38 Sh L 20 R one t / 7 eight Fue. 2