SU822192A1 - Interface testing device - Google Patents

Description

(54) DEVICE FOR INTERFACE CONTROL

one

The invention relates to computing and can be used to monitor and locate faults associated with the disruption of the sequence of control signal exchange between the channel and the peripheral control device.

A device for controlling interface signals is known, which contains a control node, information buses, control signal buses, and special buses on which a signal appears in the event of an error due to incorrect: parity on the information buses during the exchange of control information or data 1 .

However, this device does not allow to detect malfunctions associated with incorrect sequence of control signals themselves.

The closest in technical essence and the achieved effect is the device for controlling the interface of the channel EU-4035 (TS53.057. 003.TO), containing input selectors whose inputs are the inputs of the device, the error presence selector, the error trigger, and the outputs

input selectors are connected to the corresponding inputs of the error selector, the output of which is connected to

trigger

installation input in

error, the error reset signal bus is connected by the installation input to the error trigger o, and the error trigger output is connected to the error signal bus.

0 parity on information buses provides control of the reliability of control signals 2.

However, this device does not accurately determine the address.

5 mistakes.

The purpose of the invention is to increase the efficiency of control by localizing the fault.

The goal is achieved

0 in that the device for controlling the interface containing input selectors, whose inputs are the device inputs, the error signal bus, the error signal reset bus,

5, an n-bit error code register and an OR element are entered, the outputs of the input selectors are connected respectively to the single bit inputs of the error code register, the fault signal reset bus 0 is connected to

the zero-bit inputs of the error code register f, the outputs of the error code register are connected respectively to the input "| and the OR element and are outputs of the device error code, the output of the OR element is connected to the error signal bus,

FIG. 1 shows a diagram of the device; in fig. 2 - the algorithm of operation of the automaton of the interface unit, which generates a sequence of control signals. The device contains input, selectors 1-4, error code register 5, error signal reset bus 6, input buses 7, element OR 8, error code buses 9-12, and bus 13. error signal.

To clarify the operation of the device. Let us describe the sequence of sampling by the channel of the peripheral device, carried out in accordance with OCT4, GO.304. 000

The initial sampling sequence: a peripheral device address code (state B of the interface) and ADRC (address from the channel) indicating the device on the address buses (state o) are outputted to the output buses of the channel. In this state, a VBRK signal is issued (sample from the channel) at which the device compares the address given to the output bus with its own address. If the addresses are not equal, then the device responds with a BREAK signal (inverse of the sample — state C). In case of equality of addresses, the device responds

Thus, in the process of performing the sequence, sampling of the peripheral device, the channel and the interface unit with the peripheral devices exchange control signals accompanying various information on the busbars.

signal SLAVE (subscriber work). The channel resets the ADRC signal and waits (state E) from the ADRA signal device (subscriber address), with which the device indicates that the device address code has been issued to the input busses of the channel.

The appearance at this moment of other signals of the peripheral device UPRA (subscriber state), INFA (subscriber information), DANA (subscriber data), VIBRA (inverse sampling) are erroneous,

As an example, let us consider the operation of the device for controlling the interface in the state E of the automatic interface unit. In this state, an ADRA signal is expected. If the expected signal arrives, the automaton enters state-F. If a false signal arrives, for example, UPRA, then the conjunction of the F state and this false signal causes the error code of the 4th register of register 5, which leads to the appearance of 9-12 on the tires 9-12, which determines that the peripheral device There has been a false signal to the UPRA instead of the ADRA.

On bus 13, an error signal appears when setting at least one trigger to an error code register. In other states of the automaton of the interface block, the appearance of spurious signals leads to the formation in register 5 of the corresponding error code, which is presented in the table.

The sequence of signals and the nature of the transmitted information

strictly defined. Violation of the sequence as a result of any malfunction leads to an unpredictable disruption in the operation of the computer due to compensated distortion

the meaning of the information received in the channel. The device for controlling the interface allows shortening the search time for a malfunction by forming a special code that indicates a malfunction.

Claims (2)

1. The patent of France 2284927, cl. G 06 F 11/10, 1976. 2. Device for controlling the interface of the channel EU-4035 (Ц53.057.003.TO) (prototype).