SU1594549A1 - Device for interfacing multiple-machine complex with check means - Google Patents

Abstract

The invention relates to computing, in particular, to interfacing and switching devices, and can be used in the design of multi-machine computing systems with increased reliability. The aim of the invention is to increase the reliability of operation of the multi-machine complex. The device contains a block of registers of line numbers, a block for decoding line numbers, a block of pulse shapers, a block of elements I, selectors of codes of numbers of lines, selectors of codes of numbers of a computer, switching blocks of the first and second groups. The decoder of the number of the testing computer, the comparison circuit, the AND-NO element are entered into the device. 1 hp f-ly, 3 ill.

Description

The invention relates to computing and can be used to build multi-machine computing systems.

The aim of the invention is to improve. reliability of multi-machine complex operation.

Figure 1 shows the block diagram of the device; figure 2 is a functional diagram of the switching unit; FIG. 3 is a block diagram of a multi-machine complex using a device.

The device contains a block of 1 registers of line numbers, a block of 2 decryption (decoder) of numbers of lines, a block of 3 pulse formers, a block of 4 I elements, a switching unit 5 of the first and second groups, a selector 6 of codes for the numbers of lines, a selector 7 of computer codes of numbers groups of peripheral information inputs of the device.

tires 9 and I about groups of computer informational outputs and device inputs, bus 11 groups of peripheral information, IOnIa rx outputs of the device, input 12 of the assignment switching code, input 13 of the setting of the device test mode, input 14 of the computer, input 15 setting the number of the testing computer, the decoder 16 of the number of the testing computer, comparison circuit 17, I-NE element 18, input 19 cycles of reception of the simulating code, device configuration output output bus 20, synchronization input 21, test output group 22, test resolution input 23the input path of communication with the computer, the outputs 24 of the decoder 16 signals enable verification of the output path of communication with the computer.

The switching unit 5 (figure 2) contains the register switching code 26 choice

with

4 01

4ih SB

31

The controls, the input switch 27 and the multiplexer 28 controlled points The multimachine complex (FIG. 3) contains the interface 29, the complex control device 30 and the computer group 31, each of the tires of i8 and 11 are connected to the leriperity device groups.

I The device works in the following way.

Blocks 5 are controlled by codes, respectively, Line number and Computer number, received from the selector outputs | b and 7, Line number codes are specified in the | registers of unit 1 when the device operates; STA in the system, then using unit 2 decoders to the drivers of unit 3 are generated codes; computers; and are fed to the inputs of selectors: 6 and 7; 5 other inputs of which are provided for receiving signals to receive simulated codes; switching from input 12 in the device check mode specified by the signal from input 13.

A: Determination to be checked; connections are made according to the state of the signals at input 14, which are signs of non-execution of individual computers in the system. The test mode is 1-: and unused blocks 5 is set directly from the inputs 14 for blocks 5 of the first group, and for blocks 5 of the second group - by the outputs of block 4, which generates installation signals in the test section of the selected block 5 , iioro is not active in the system. Switching codes from the outputs of the selectors b and 7 are received by the IB register 25 of the selected block 5 sig n. Received 19, generated at the time of the configuration change. The decoder 26, which when the unit 5 in the system provides the choice of one of. switching directions 8 (10) to form output 9 (11), in the test mode of the switch unit, it blocks reception of signals from inputs 8, 0 and simulates the signals at these inputs inside block 5. Depending on the code entered by the test program into register 25 , one of the input signals 8 or 10 is simulated, respectively. The checking program completes the polling and comparison of the states of the outputs of the 22 blocks 5 with the expected states. The deviation from the reference value of the signals monitored

0

five

0

five

45494

points of this block is considered a malfunction of block 5.

Thus, the device provides automatic detection of 5 unused switching blocks 5 and their sequential checking from any of the unused computers by automatically iterating through unused blocks, simulating operation modes and polling monitored Stocks without interrupting the functioning of the affected switching blocks 5. The input 15 sets the number of the testing computer not active in the active mode of the complex, and the comparison circuit 17 determines the equality of the number of the testing computer with the simulation code of the computer number entered by the testing program on input 12 into the register 25. The equality signal at the output of the comparison circuit 17 means that the channel output of the testing computer (device input 10) can be covered by the test system of any tested block 5. To do this, block the reception of input 10 into the switching block 5 selected for the test (in test mode The holes 10 blocks 5 of the second group are automatically blocked). This is provided by generating a signal at the output of the NAND 18 element and using the signal at the output 23 of resolving the input path of the communication with the computer, set by the test program, if the number of the testing computer is equal to the code of the computer at the input 12. Once active The check mode signal on bus 20 for the selected block 5 is suppressed, the check program sets the reference codes at the output of the input / output channel of the computer (input 10) and controls these codes at the output 22 of the device, which makes it possible to cover with check not only blocks 5 second group but also the corresponding communication path of the input bus 10 and the transmitting elements of the input-output channel of the computer. For coverage; checking output bus 9 uses the corresponding output 24 of the decoder 16, which is active when the number of the testing computer matches the number of the selected block 5 of the first group (the outputs 24 are analyzed by the testing program at the output 22 of the device). output bus 9, which are connected to the input

0

five

0

five

0

five

The input-output channel of the testing computer 31 can be checked directly in the equipment of the input-output channel of the testing computer, which is done by the testing program. Thereby, the test bus 9 and receiving elements of the I / O channel of the testing computer are covered by the test.

Thus, the test covers the communication path of the device with the computer, which is a difficultly walled fault area in the absence of direct control.

Claims (2)

Invention Formula A device for interfacing a multi-machine complex with a control containing a block of line number registers, output connected to the first information inputs of the line number decoder and the line number code selector, the output of which is connected to the address inputs by the switching unit of the first group, the code number selector of the computer whose first information input is connected via a block of computer number code generators to the direct output of the decoding unit of line numbers, and the output to the address inputs of the second group switching units, allowing the inputs of which are connected to the output of the I block, the first input connected to the inverse output of the decoding unit of line numbers, the first outputs of the switching blocks of the first and second groups form, respectively, groups of information machine and peripheral outputs of the device, and the second outputs form a group of control outputs of the device. . The second information inputs of the computer code number and line code lecturers are connected to the input of the setting of the device switching code, and the control inputs are connected to the input of setting the device test mode, the second information input of the line number decryption unit The computer of the device and connected to the enable inputs of the switching units of the first group, the group of information inputs of which are connected to the group of information peripheral inputs of the device, and the clock and synchronization inputs correspond to enno to the input reception cycles simulating input synchronization code and ten 15 20 25 0 five 0 five 0 five devices and clocking and synchronizing inputs of the switching units of the second group, group information; . The input inputs of which form a group of information machine inputs of the device, the input of the block of registers of line numbers and the output of the block of elements AND are respectively the input of the configuration and the output of the configuration state of the device, characterized in that, in order to increase the confidence in the operation of the complex, decoder number testing. The computer, the comparison circuit and the NAND element, the second input of the AND block of the elements AND connected to the output of the NAND element, the first input of which is the input of the input path test resolution, communication with the computer, and the second input connected to the output of the comparison circuit connected the first input to the task input: .. simulating the switching code of the device, and the second input - to the input setting task number of the testing computer device and the input of the decoder number of the testing computer, the group of bit outputs of which are connected to the information inputs of the switching units of the first g uppy. . 2. The device according to claim 1, which is: tl and - and the fact that each switching unit of the first group contains a multiplexer of controlled points, an input switch, a group of information inputs and an output of which are respectively a group of information inputs and the first output of the block, the decoder of the choice direction, the output connected to the control input of the input switch, and the switch code register, the output connected to the first information inputs of the multiplexer of controlled points and the direction selector decoder, the second info The mapping inputs of which are connected to the block enable input, the outputs of the direction decoder and the input switch are connected to the third and fourth information inputs of the controlled points multiplexer, the fifth information input, the control input and output of which are the corresponding input of the synchronizing input, respectively. and the second output of the block. Fri W Figg 22 Bin) 8M) 8t (Yut}