SU519754A1 - Time-division multichannel television signaling system - Google Patents

Description

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The invention relates to a time-division multichannel television signaling device for transmitting information from remotely monitored objects to an information collection point via wired communication lines.

Systems are known that contain sealing devices, the signal inputs of which are connected to monitored objects, and the outputs via a communication line to a receiver made on a clock generator, the output of which is connected to the first input of the local control unit and through the clock generator to the first shaper inputs. synchronizing pulses, pulse distributor and interface block. The output of the sinus pulse generator is connected to the first input of the control unit and to the second inputs of the interface unit, the local control unit and the pulse distributor, the output of which is connected to the first inputs of the first and second registers and the inverse numerical conversion unit. The third input of the interface through the first valve is connected to the unit of forming a single signal, through the second valve to the input of the third valve, to the second input of the inverse numeric conversion unit and to the first output of the second register connected via the fourth valve to the input of the terminal conversion unit This valve is connected to the output of the first register and to the first inputs of the first comparison unit and through a double valve to the second input of the second register and to the outputs of the third and seventh valve, one input of which is connected yield numerical inverse transform block. The output of the interface unit is connected to the second input of the first comparison unit, through the amplitude discriminator to the first input of the logic processing unit, through the eighth gate directly and through the serially connected numerical code conversion unit and the ninth gate to the second input of the first register, the second output of the associated with one of the inputs of the zero code decoder. The other input of the latter is connected to the first input of the interface unit, and the output to the corresponding input of the control unit, one output of which is connected to the first input of the memory unit, the second input of which is connected to the output of the local control unit, to the second output of the second register, the first the output to the corresponding input of the control unit, and the second to the second input of the logic processing unit, the first output of which is connected to the corresponding input of the control unit. One group of outputs of the control unit is connected to EXOAaivi of the first, second, third, fourth, d, sixth, seventh, eighth and ninth gates, local control unit, first comparison unit and pulse distributor. The disadvantage of these systems is the possibility of failures in the reception of information due to the occurrence of interference on the communication line. The purpose of the invention is to improve the noise immunity of the device. This is achieved by the fact that emergency blocks, a second comparison block and additional valves are inserted into the receiving device. The output of the first comparison unit is connected through the tenth, eleventh and twelfth valves, respectively, with the inputs of the first emergency unit, the terminal conversion unit and the control unit, the outputs of the first emergency unit with the second inputs of the eleventh and twelfth valves, the logic processing unit inputs, respectively, through the thirteenth and the fourteenth valves are with the fourth input of the memory unit. The second output of the logic processing unit is connected via the fifteenth, sixteenth and seventeenth gates respectively to the inputs of the second emergency unit, the terminal conversion unit and the control unit, the outputs of the second emergency unit to the second inputs of the sixteenth and seventeenth gates, and the third output of the logical processing unit through the eighteenth The nineteenth and twentieth valves are connected to the corresponding inputs of the third emergency unit, the terminal transformation unit and the control unit. The outputs of the third emergency unit are connected to the second inputs of the nineteenth and twentieth valves, the second comparison input to the output of the interface unit, the other to the first output of the second register, and the output to the corresponding inputs of the terminal conversion unit and the control unit, the second group of outputs which is connected respectively to the second inputs of the tenth, thirteenth, fourteenth, fifteenth and eighteenth gates, to the corresponding inputs of emergency units and to the third input of the second unit compare. This allows the receiver to register an emergency situation to restore in the communication line the signals preceding the reception of information about the occurrence of this situation, and to output information about the occurrence of this situation only if it is re-registered, which significantly reduces the likelihood of a false indication the emergency device as a result of receiving transient signals from the communication line. The drawing shows a diagram of a multichannel system. It includes a group of peripheral sealing devices 1 and a receiving device 2, interconnected by a line 3c. Receiver 2 contains a 4-stroke pulse generator, a synchronizing pulse shaper 5, a synphating pulse shaper 6, a pulse distributor 7, an interlock unit 8, a numeric code conversion unit 9, registers 10 and AND, a zero-code decoder 12, blocks 13 and 14 comparing, block 15 inverse numerical code conversion, control block 16, terminal transform block 17, amplitude discriminator 18, logic processing block 19, memory block 20 with local control block 21, unit 22 of generating a single signal, and 23, 24 and 25 emergency situation dictors (blocks) and control valves 26–45. The generator 4 clock pulses are connected to the inputs of the generator 5 synchronized, their pulses and the local control unit 21, the generator of the generator synchronized 1, and their pulses to the inputs of the converter 6 of the synphating pulses, the distributor of 7 pulses and to one of the inputs of the interface unit 8 with the communication line, the output of the generator of the synphating pulses to one of the inputs of the local control unit 21, to the clock input of the control unit 16, one of the distributive inputs A pulse generator 7, the control input of the decoder of the 12-zero code and to one of the inputs of the interface unit 8 with the communication line. The output of the pulse distributor is connected to the clock inputs of the registers 10 and 11, the block 9 of the numerical code conversion and the block 15 of the inverse numerical code conversion. The output of the interface unit 8 with the communication line is connected to the input of block 9 of the numerical code, the input of the amplitude discriminator 18, the inputs of blocks 13 and 14 and the valve 30 to the input of the register 10, the output of the block; numerical code conversion through the fan., 29 - to the input of the register 10; parallel output of the register 10 - to the input of the decoder ll of the zero code. A serial output of this register is connected to the second input of the comparison unit 13, through the valve 31 to the input of the register 11 and through the valve 28 to the input of the interface 8 unit with the communication line. The parallel output of the register 11 is connected to the address input of the memory unit 20, the serial output of this register is connected to the input of the inverse numerical code conversion unit 15, the second input of the comparator unit 14, through the gate 34 to the input of the terminal conversion block 17, and to the input 27 the interface 8 unit with the communication line and through the gate 32 with the input of this register, the output of the reverse code numeric conversion unit through the valve 33 - with the input of the register 11. The output of the block 14 is connected to one of the inputs of the block 17 of the terminal transformation and one of -disc control unit 16 inputs.

The output of the amplitude discriminator 18 is connected to one of the inputs of the logic processing unit 19 and through the gate 44 to one of the signal inputs of the memory unit 20. One of the outputs of the memory block 20 is connected to the same signal input of the memory unit through a valve 45, which is simultaneously connected to the second input of the logic processing unit 19, and the control input of the memory unit to the output of the local control unit 21.

The output of the unit 22 forming a single unit through the valve 26 is connected to one of the inputs of the interface unit 8 with a communication line, the output of the comparison unit 13 through the valve 35 is connected to the input of the emergency indicator indicator 23, through the valve 38 to one of the starting inputs of the control unit 16 and through the valve 41 with one of the inputs of the terminal transformation block 17, the control inputs of the valves 38 and 41 with the inputs of the emergency indicator indicator 23.

The output 46 of the logic processing unit 19 is connected via the valve 36 to the input of the emergency indicator 24, through the valve 39 to one of the starting inputs of the control unit 16 and through the valve 42 to one of the inputs of the terminal conversion unit 17, the control inputs of the valves 39 and 42 to emergency indicator outputs.

The output 47 of the logic processing unit is connected via a valve 37 to the input of the emergency indicator 25, through a valve 40 to one of the start inputs of the control unit and through a valve 43 to one of the inputs of the terminal 17 of the final conversion, the control inputs of the valves 40 and 43 to the outputs of the indicator 25 emergency.

The output of the null code de-blender 12, the output 48 of the logic processing unit and the second output of the memory unit 20 are connected to the start inputs of the control unit 16, the output 49 of the control unit to the second signal input of the memory unit 20, the control outputs of the control unit to the control inputs of the gates 26 - 37, 44 and 45, as well as to the control inputs of the comparison units 13 and 14, the local control unit 21 and the distributor 7 and the installation inputs of emergency indicators 23, 24 and 25 (in the drawing these connections are conventionally denoted by the letter "K").

Block 9 of the numerical code conversion provides the addition of a numeric constant code to its numeric expression, for example, "1, inverse numeric numeric code conversion block 15 — subtraction of the same numeric constant code from its numeric expression.

The control unit 16 may be implemented as a group of shift registers, each of which is connected to its own address input, and the outputs of these registers are combined through a combinational logic circuit.

The memory block 20 may be manufactured on the basis of a random access memory.

any known construction with address structure.

Peripheral sealing devices 1 through their signal inputs 50 are connected to

controlled objects. These devices provide, upon receipt at their inputs through the link 3 of the individual address codes, the generation into the link of the individual response codes of that structure,

that both address and sporadic transmission to the communication line of messages on the facts of changes in the states of ICOHT controlled objects connected to them as a sequence of codes containing the transmission start code (consisting of one unit characters), the device’s own address code and the code displaying signal values at the device signal inputs 50 at the time of message transmission.

B as a peripheral sealing device 1 can be used, in particular, a television signaling device.

The response (as well as address) codes of all peripheral devices on the first time reference necessarily contain a single character, and this position of the code is not subjected to conversion in blocks of the number conversion 9 and inverse number conversion of code 15.

It is convenient to consider the operation of the device initially assuming that there are no signals at the inputs 50 of all peripheral devices. For convenience of consideration, it is also advisable to assume that

Peripheral links form a complete set, characterized in that the response code of each device differs from the address code of this device by an amount equal to the value of the numeric constant used in the numerical code conversion unit, and, moreover, is the address code of the other peripheral devices, and codes consisting of one single characters and one zero characters are not

are address ns for one of the perisphere devices.

The generator 4 clock pulses of the receiving device 2 generates a continuous sequence of pulses, on the basis of which the shapers of the synchronizing pulses 5 and the synphating pulses 6 generate the sequence of the corresponding pulses output through the communication line interface unit 8.

In this case, the synchronizing pulses are used to limit the temporary positions of the codes transmitted over the communication line, the siphasing pulses serve to temporarily separate these codes, and the interval between two adjacent synphating pulses forms a device operation cycle.

If, as it was stipulated, an undistorted sequence of address (response) codes is transmitted over the communication line, no signals arrive at the start inputs of control unit 16 and the signals at its command outputs are such that gates 29, 31, 35, 36, 37 and 45 are open, permitting signals are present at the control inputs of the comparison unit 13 and the local control unit 21, the control input of the comparison unit 14 is a inhibitory signal, the rest of the valves are closed, and the output 49 of the unit 16 is absent. In this case, the indicators 23, 24, and 25 are in such a state that the control inputs of the valves 38, 39 and 40 contain the enabling signals, and the inputs of the valves 41, 42 and 43 are prohibiting. Let at some point in time the address code of one of the peripheral devices is transmitted via the communication line. This code is simultaneously entered into all peripheral devices, as well as via the interface 8 unit to the communication line into the numerical code conversion unit 9, from which, increased by the value of the numerical constant, through the open valve 29 is entered into the register 10, the shift of which is provided by applying to it The clocking input of pulses from the output of the distributor 7. Thus, by the end of the transmission of a given code over the communication line, in register 10 there is a recorded code whose transmission over the communication line is expected in the next clock cycle. At the same time, the code previously recorded in register 10, i.e., equal to the code transmitted over the communication line in a given clock, is rewritten to register 11 via the open valve 31, i.e. the address of the peripheral device is written to the end of the clock in register 11 which should respond in the next measure. The next synphating pulse from the output of the imaging unit 6, which determines the beginning of the new cycle, starts the local control unit 21, which supplies the readout signal to the memory unit 20. In this case, information is read from a memory cell with an address equal to the code recorded in register 11, i.e., equal to the address code of the peripheral device whose response is expected during this cycle. It contains two identifiers, and the entry of one of them (for example, the 1st one) is entered into the logical processing unit 19 (this identifier is equal to "1 if this peripheral device responded in the previous poll cycle, and" O otherwise), and the value of the other (2nd) identifier contains “O, if the peripheral device responded correctly in the previous poll cycle, and“ 1 otherwise. Next, the peripheral device 1, which receives its address code in the previous cycle, generates the response code to the communication line, which, as before, through the matching unit 8 with the communication line and the numerical code conversion unit 9 enters the register 10. The first character of the code (always single, as it was noted) is fed into amplitude discriminator 18, from the output of which a single character indicating the presence of a signal at the output of discriminator 18 enters logic processing unit 19. If there are single signals at both of their inputs, the logic processing unit does not generate any signals at any of its outputs 46, 47, and 48. The control unit 16 also holds a zero signal at output 49, which, when fed to the control input of memory block 20, These recording signals from the output of the local control unit 21 are recorded in the cell with the address equal to the address code corresponding to the peripheral device in this cycle "1 from its own output through gate 45 and" About from the output 47 of the control unit, i.e. the values of both are ifikatorov is unchanged compared to the previous ones. The code generated by the peripheral device also goes through the interface unit 8 to the communication line to one of the numerical inputs of the comparison unit 13, the other input of which simultaneously receives the code from the register 10 output. At the same time, if the peripheral device responds correctly, both of these the code is matched, and the comparison unit 13 produces no signals. The code from the output of register 10 through an open valve 31 is rewritten, as in the previous cycle, into register 11. Thus, the device operates when, during each subsequent cycle, a code different from the code transmitted in the previous cycle is transmitted to the numeric one a value equal to the numeric constant used to convert the codes in the code conversion block 9, i.e., when no information is received through peripheral devices from monitored objects, and all peripheral devices function normally. If there is no response from any peripheral device (caused by the failure of this device, disruption of the communication line or disconnection of this device from the communication line), the signal at the input of the amplitude discriminator 18 is not received in the corresponding clock at the first time position. From the output of the amplitude discriminator 18 to the input of the logic processing unit 19, a zero signal is applied, while from the output of the memory unit 20 to its other input passes a single value of the identifier of the on state of this peripheral device. The logic processing unit generates a signal at its output 46, which comes through the open valves 36 and 39 to the input of the indicator 4, an emergency situation, one of the starting turns of the control unit 16. At the same time, the front of the signal is launched by the control unit, and the rear edge is the cocking of the indicator 24, the signals from the outputs of which lock the valve 39 and turn off the valve 42. The single signal from the output of the memory block 20 through the valve 45 enters its signal input and records after it arrives at the control input of the memory block, the recording signal from the output of the local control block 21 is still the unit value of the corresponding identifier. The control unit 16, after receiving the start signal from the output 46 of the logic processing unit 19, issues command signals that unlock the gates 26 and 32 and the gate gates 31, 35, 36, 37 in this cycle. As a result, in this cycle, the single signal generator is output through an interface unit 8 with a communication line to the communication line 3 of a code consisting of only single characters, the input of register 11 is disconnected from the output of register 10 and connected to its own output, and the inputs of indicators 23, 24 and 25 are blocked. At the same time, the control inputs of the comparison block 13 and the local control unit 21 are given prohibitory signals that prevent them from operating in this cycle. At the end of the cycle, the code consisting of single characters from the communication line through the interface unit 8 and the numerical code conversion unit 9 is rewritten into register 10, and the address code of the peripheral device whose response is was not received in this cycle, it is restored in register 11. At the time of forming the next synphating pulse determining the beginning of a new cycle, the output of the zero-code decimator 12 produces a signal arriving at the starting input of control unit 16 and together With a synphating pulse arriving at the clock input of the control unit from the driver output, the command signals at the output of the control unit are switched in such a way that in the next clock cycle the valves 26 and 29 are locked and the valve 30 is unlocked. The remaining command signals in this clock cycle do not change. Thus, within this cycle no codes are transmitted over the communication line (the zero code is transmitted more precisely), since no peripheral device responds to the single code transmitted to the previous one, and the 26, 27, 28 gate connectors devices 2 with line 3 are closed. In this case, the zero code through the interface 8 with the communication line and the valve 30 without conversion goes to the register 10, and the address code of the unresponsive peripheral device is again restored in the register 11. At the clock step, the numeric code 12 is reversed by the next synphating pulse, the signal c the output of which is again guessed at the start input of the control unit and together with the in-phase pulse arriving at the clock input of this block. switches the command signals at the outputs of this unit so that valve 30 is locked and valves 29 and 27 are unlocked. As a result, in the next cycle, the communication line through the interface 8 with the communication line and the valve 27 from the register 11 displays the address code of the peripheral device that did not answer earlier, the code being entered through the block 9 of the numerical code conversion and the valve 29 into the register 10 is converted in it to the response code of this device. In register 11, the address code of the same device is again restored to the end of the clock cycle. Thus, in this tact, in the communication line and in the registers of the signal and output register, the situation preceding the moment of registration of the absence of a response from this peripheral device is completely restored. In this case, the control unit 16 removes the inhibit signal from the control input of the local control unit 21. If now in the next clock cycle at the place of the first character of the response code of the peripheral device, a null symbol again arrives at the receiving device 2, the output 46 of the logic processing unit 19 again generates a signal, which this time through the gate 42 is fed to the input of the terminal conversion unit 17, indicating the fact When the device registers a situation, the peripheral device is not responding. In this case, the control unit closes the gates 32 and 45 in this cycle, and the gates 28, 31, 34 and 44 unlock, as a result of which the zero value of the identifier of the enabled state of the peripheral device is written to the memory unit 20 from the output of the amplitude discriminator 18 A short-circuit register register 10 displays the response code of the peripheral device that did not respond in a dunk clock, which is the address code of another peripheral device. The address code of the non-responding peripheral device is rewritten into block 17 of the terminal conversion, and the address code of the peripheral device 1, which must respond in the next cycle, from register 10 to register 11. The control unit also provides the tap signal to the installation inputs of all indicators 23, 24 and 25 emergency situations, after which in the next cycle it restores the original value of all command signals, and the device continues its work on the described mode, when no information from the peripheral devices in the receiving device does not arrive. The final conversion unit 17 carries out either a visual indication of the data entered into it, or their conversion, convenient for further use in any recording devices. If confirmation of an emergency situation does not occur (the peripheral device responds correctly when it is being recalled) the signal at the output 46 of the logic processing unit 19 is not generated and, accordingly, does not flow through the valve 42 into the terminal conversion unit, which prevents the code unit from receiving the output 11 from the register. Further, in subsequent cycles of the device operation, in the case of repeated absence of signals from the output of this peripheral device at the moment of passing the first time position of the code to block 19, the logic tion from the output processing unit 20 is supplied to the memory has the value zero identifier on state of the peripheral device, which in combination with the zero value of the signal at the output of an amplitude discriminator 18 cause a phenomenon of signal 47 at the output of block 19, the logical processing. This signal, falling on the corresponding start input of the control unit, in turn, results in the formation at its command output of a signal that unlocks the gate 28. Thus, each time, the missing response code in the communication line is replaced with a code outputted from register 10 , and in the terminal transformation block 17, the disconnection information of this non-peripheral device, which is now redundant, is not received. If in one of the subsequent operation cycles of the device, this peripheral device again returns the response code to the communication line (the emergency situation is resolved), a first signal is generated at the output of the amplitude discriminator 18, which, in combination with the zero value of the identifier arriving from memory block 20, causes the appearance of a signal at the output 48 of the logic processing unit 19. This signal goes through the open valve 40 to the starting input of the control unit and to the input of the emergency indicator 25, which is driven by the falling edge of this signal, the unlocking valve 43 and the locking valve 40. Further operation of the device is as follows. The signals from the command outputs of the control unit lock the valves 35, 36 and 37, fixing the states of the indicators 23, 24 and 25, unlocking the valve 26, ensuring that a single code is output to the communication line from the single signal generator, and the valve 31 is opened , ensuring that the address code of the responding peripheral device is restored to the end of the clock cycle in the register 11. Next, as in the described case of the peripheral device stopping response, the zero code is indicated by the null-code decimator 12 After the single code passes through it, the address code of the peripheral device, the response of which was previously received, is output from the register 11 to the communication line. In the case of this device's repeated response, the output from the output 48 of the logic unit 19 through the gate 43 enters the final conversion unit, indicating the situation that the "peripheral device is turned on." In memory lock 20, by unlocking the valve 44, the unit identifies the enabled state of the peripheral device and the address code of this device is restored from register 11 through valve 34 to end conversion unit 17, after which the tamper signal is transmitted to the installation inputs of indicators 23, 24 and 25, and on the command outputs of the control unit, the original combination of command signals is restored. If the previously detected situation (the peripheral device denies) is not confirmed, the signal at the output 48 of the logical processing unit does not occur and does not flow through the gate 43 to the input of the terminal conversion block 17, which therefore does not accept the address code entered into it from the register 11. In this case, the control unit unlocks the valve 28, through which the response code of the disconnected peripheral device is output from the register 10 to the communication line, after which the operation of the device proceeds in an orderly fashion. In the event that any peripheral device responds with an incorrect code (but containing "1 in the first temporary position), this fact is indicated in the receiver with a signal from the output of the comparison unit 13, which detects a mismatch of the codes arriving at its inputs from the outputs of the interface 8 with the communication line and the register 10. Since this fact can be finally established by the block 13 only at the end of the clock, in register 11 by this moment the correct response code of the peripheral device appears, which in this case responded wrong. The output signal from the comparison unit 13 through the valve 38 enters the starting input of the control unit 16 and through the valve 35 to the input of the emergency indicator indicator 23, which is charged by the falling edge of this signal, opening the valve 41 and the locking valve 38. Next, in the next cycle, the control unit similarly to the previous cases, the valve 26 is unlocked and a single code is output to the communication line, which "attenuates in the communication line the response code of the peripheral device that may occur there if any of the peripheral devices invalid response code peripheral device transmitted in the previous cycle, as its address code. In the same cycle, by turning on the valve 33 and turning off the valve 31, the response code of the peripheral device that responded incorrectly is transmitted from the output of the register 11 through the block 15 inverse numerical conversion to its input, so that the peripheral address code devices that

In the next cycle, as in the previous cases, null-code decimator 12 analyzes the presence of information transmission over the communication line after passing a single code through it and if there is no transmission, the output signal from the decoder 12 receives the input of the control unit. After that, in the next cycle, the address code of the peripheral device that answered incorrectly is output to the link from the register I via the gate 27 and the interface unit 8, and the same CODE is restored at the end of the cycle in register 11, and to register 10 through valve 29 and the finishing unit 9, the response code of this peripheral device is recorded.

If in the next cycle the response code of the peripheral device transmitted via communication line 3 and its response code recorded in the register 10 of the register 10 again appear to be mismatching, the comparison unit 13 generates a signal coming through the gate 41 to the terminal 17 of the Terminal Transformation and indicating a fact Emergency Detection The peripheral device responds incorrectly. The address code of this device from register 11 is output to the terminal conversion unit, and the control inputs to the installation inputs of indicators 23, 24 and 25 are given a signal that sets them to their initial state. In addition, the control unit 16 generates a single signal at the output 49, with the result that when the recording signal is sent to the control input of the memory block 20, a single value of the second identifier is written into the cell with the address equal to the address code of the peripheral device that responds incorrectly.

If, as in the cases described earlier, the emergency situation is not confirmed, i.e. the codes applied to the inputs of the unit. 13 comparisons turn out to be the same, the signal at its output is not generated and does not arrive in block 17 of the terminal transform. As a result, the address code of the responding incorrect peripheral device is not accepted by this unit, and the control unit in the next cycle sets the indicators 23, 24 and 25 to their initial state, after which the operation of the device continues in the order described. In this case, in the memory block 20, the zero value of the second identifier is stored.

In cycles followed by a cycle in which an incorrect response of one of the peripheral devices is registered, in the tact in which the response code of this device must be received, the output of the memory unit in the control unit receives a single value of the second identifier, resulting in the control outputs of the control unit generate signals that unlock the valve 26 in this cycle and turn off the comparison unit 13. At the same time, a code consisting of one single characters and an invalid response code of the failed peripheral is outputted to the line 22 and from the mapper 22 of the single code via the gate 26 and the interface unit 8 of the communication line. The correct response code of this device is rewritten from this register in this cycle.

10c register 11.

In the next cycle, the valves 26, 29 and 31 are locked, and the valves 30 and 32 are unlocked, resulting in a code that contains only null characters on the communication line, this code is written to the register 10 through the valve 30, and the correct failed peripheral response code. The zero-code decoder 12 at the time of forming the next synphating pulse analyzes the presence of a zero code in register 10, after which, from its output, a signal is sent to the control unit, which

At the next cycle, valve 30 is locked and valves 27 and 29 are unlocked. As a result, the response code of the failed peripheral device is output to the communication line from register 11, this code is transferred to register 10 through block 9 and the valve 29 is converted to register 10. code of the next peripheral device, and in the register

11, the response code of the failed peripheral is still stored.

In the next cycle, all the valves return to their original state. Thus, the device makes it possible to add incorrect response codes that have failed but not disconnected from the communication lines of the peripheral devices without outputting each time to the terminal transform unit the information on the failure of these devices.

At the end of each cycle of the device

a peripheral device that responds last in a loop, the response code consisting of one single characters is output to the communication line. This code, posun through block 8 of conjugation with the communication line, block 9 numerical

conversion code 9 and the valve 29 in the register 10 is converted into a zero code in it. At the end of the cycle, a descrambler 12 of the zero code is interrogated by the next in-phase pulse, the signal from the output of which

into the control unit.

In the next cycle, the control unit locks the valve 29 and unlocks the valve 30, a zero code that occurs due to the absence of responses from peripheral devices, is recorded without conversion to the register 10, and the decoder 12 again generates a signal to the control unit. In the next cycle, the control unit performs the reverse switching of the valves 29 and 30, and the zero code, newly transmitted over the communication line, is written to the register 10 through the block 9 of the number conversion code in the form of the address code of the peripheral device,

Claims (1)

interviewed in each cycle first. Next, in the next clock cycle, the valve 28 is opened, and this code from register 10 is output through the interface unit 8 to the communication line, simultaneously over the valve 31 is rewritten to register 11, and thus the new cycle of operation of the device begins. When any peripheral device occurs at one of the inputs 50, a signal from the object being monitored, this device transfers to the communication line a code consisting of only single characters. This code through the interface unit with the communication line, the numerical code conversion unit and the valve 29 enters the register 10 as a zero code, as a result of which a signal arriving at the control unit is generated in the sheep of the zero code decoder. As in the case of the end of the cycle, the control unit locks the valve 29 and unlocks the valve 30 at the next cycle. At the same time, the peripheral device receiving the signal at input 50 outputs its own address code, which is always different from zero, in the communication line. This code without conversion enters the register 10 and, at the time of the clock cycle, the zero code decoder does not generate a signal. As a result, in the future, the device is operated according to a program that differs from the program of transition from one cycle to another. In the next cycle, the same peripheral device transmits a code describing the value of the signals at all its inputs 50. This code is also copied to register 10 without conversion, and the address code of the peripheral device 1 transmitting information is rewritten from register 10 to register I. During this cycle, the control unit generates signals to the installation inputs of the indicators 23, 24 and 25, thereby preventing their influence on the further reception of the message from the peripheral device. In the next cycle — by unlocking the valve 26, a code consisting of single characters is output to the communication line, and in this cycle the shift of registers 10 and 11 is slowed down by sending a command signal from the output of the control unit to the control input of the distributor 7, due to which the registers 10 and I retain the codes previously recorded there. In the next two cycles, the peripheral device, which received the signal at input 50, carries out a repeated-transmission of a message consisting of its address code and a code describing the values of the signals at its inputs 50. At the same time, the shift of the registers 10 and AND is again turned on, and also allowing signals to the valve 34 and to the input of the unit 14 of the comparison. Via valve 34, the peripheral device message is rewritten to the terminal conversion unit, and the unit produces a signal at the end of the second cycle if during both clock cycles all signals fed to its inputs from the register output I and from the output of the interface unit coincide with i.e. if the retransmitted message matches the first one. A signal from the output of comparator block 14 indicates the presence of an emergency situation, the state change of the monitored object. After that, by transmitting the zero code to the communication line in the same way as it was done during the transition from cycle to cycle, the device proceeds to a new peripheral polling cycle. The same code performs a translation to the state of passive pick-up of the peripheral device that transmitted the message. In case when transmitting re; communication, it does not coincide with the first (i.e., the first or second message has been exposed to interference to the communication line), block 14 does not emit a signal, and the device continues to operate in the mode of recalling the peripheral device that transmitted the message until two The transmitted messages will not match, which ensures high reliability of the received messages. Multi-channel tele-signaling system with time division channels containing sealing devices, signal inputs of which are connected to monitored objects, and outputs through a communication line are connected to a receiver made on a clock generator, the output of which is connected to the first input of a local control unit and through driver of synchronizing pulses with the first inputs of the generator of synphating pulses, pulse distributor and interface block, output f The synphating pulse loudspeaker is connected to the first input of the control unit and to the second inputs of the interface unit, local control unit and pulse distributor, the output of which is connected to the first inputs of the first and second registers and the inverse numerical conversion unit, the third input of the interface unit is connected to the first gate to the unit of formation of a single signal, through the second valve to the input of the third valve, to the second input of the block of the inverse numerical conversion and to the first output of the second register, connected through the fourth valve to the input of the terminal conversion unit, through the fifth valve to the output of the first register and to the first inputs of the first comparison unit and through the sixth valve to the second input of the second register and to the outputs of the third and seventh valve, one input of which is connected to the output of the block inverse numerical conversion, the output of the interface unit is connected to the second input of the first comparison unit, through the amplitude discriminator - to the first input of the logic processing unit, through the eighth gate directly and through Consequently, the connected numerical code conversion unit and the ninth gate are connected to the second input of the first register, the second output of which is connected to one of the inputs of the decoder of the bullet code, the other input of which is connected to the first input of the interface block, and the output to the corresponding input of the control unit the output of which is connected to the first input of the memory unit, the second input of which is connected to the output of the local control unit, to the second output of the second register, the first output to the corresponding input of the control unit, and the second to the " the second input of the logic processing unit, the first output of which is connected to the corresponding input of the control unit, one group of Kofoporo outputs connected to the inputs of the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth gates, local control unit, first block comparison and pulse distributor, characterized in that, with a view to increasing the reliability of the system, an emergency situation block, a second comparison block and additional valves are inserted into the receiving device, and the output of the first block a comparator connected through tenth, eleventh and twelfth valves respectively to the inputs of the first block of emergency, block the conversion of the terminal and the control unit, the outputs of the first emergency unit are connected to second inputs of the gates of the twelfth eleventh II, inputs a logical processing unit respectively by the thirteenth and fourteenth gates are connected to the fourth input of the memory block, the second output of the logic processing block is connected via the fifteenth, sixteenth and seventeenth gates respectively to the inputs The second emergency unit, the terminal conversion unit and the control unit, the outputs of the second emergency unit are connected to the second inputs of the sixteenth and seventeenth gates, the third output of the unit logic processing is connected through the eighteenth, nineteenth and twentieth valves to the corresponding inputs of the third emergency unit, the terminal transformation unit and the control unit, the outputs The third emergency unit is connected to the second inputs of the nineteenth and twentieth gates, the input of the second comparison unit is connected to the output of the interface unit, and the other to the first output of the second register, and the output is connected to the corresponding inputs of the terminal transformation unit and the control unit, the second group of outputs of which are connected respectively to the second inputs of the tenth, thirteenth, fourteenth, fifteenth and eighteenth gates, to the corresponding inputs of the emergency unit and to the third input of the second comparison unit. 50. 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