SU478346A1 - Time Division TV Alarm System - Google Patents

Description

A single signal source is connected to the input of the interface unit, with the second input of the sixth controlled valve. } ia of FIG. 1 shows the block diagram of the device; on fit. 2 - time diagrams of his work. The device contains a group of peripheral devices 1 and a receiving device 2, connected by a mei-sd line of communication 3. Each peripheral device 1 contains, in turn, a unit for receiving phase 4 and synchronization 5, pulse distributor 6, shift register 7 , address code 8 decoder, control unit 9; the driver of the response code 10 and the controlled valve 11. npiiG; .iiiOe device 2 contains the interface unit -12, the number conversion unit 13, the shift registers 14 and 15, the comparison unit 16, the control unit 17, the clock generator 18, the synphating pulse driver 19, the pulse distributor 20, the terminal transform unit 21, the single source I2, the controlled gates 23-28, the outputs of the control unit 29-32. The device consists of N peripheral devices 1, each of which has its own address code and response code, the decoder of address code 8 and the drivers of response code 10 of these devices are designed in such a way that the edal and response codes of one device 1 always differ from each other. from each other one numerical value of the velgchin (for example, 1). 1, the response code of the first peripheral device 1 is the address of the second peripheral device device 1, the response code of the second peripheral device 1 in; The address code of the third peripheral device is 1 nt, a., and the code containing one single characters is not addressable for either of the peripheral device. During operation of the device, the synchronization generator b: 1 nx pulses 18 are generated a sequence of pulses (see, flash, 2, a) which simultaneously enters the inputs of the generator of syn-fjiaanpyioffijfx pulses 19, which form its sequence of sip-phasing HMnyjLbCOB (see fig. 2, b), distribute .p pulses 20 and through the matching unit wives 12 in lshp-gyu link 3, from where through the block 5 sinhronizapyi receiving peripheral devices 464 1, it enters to the inputs of the distributor 6 pulses j these devices. The sequence of synphasing pulses from the output of the synphating pulse generator 19 is fed to the input of the pulse distributor 20 and simultaneously through the interface unit 12 to the line 3, from where it receives the peripheral devices 1 to the inputs of the pulse distributors 6 of these devices. As a result, at the outputs of the distributors b and 2O, the sequences shown in FIG. 2, c. Further consideration of the operation of the device is conveniently carried out, considering that in tact A (see Fig. 2), a code, for example, 1001 (Fig. 2, d), is transmitted over the communication line. The transmission is carried out by the lower bits ahead at the same time positions at which the sequence pulses are formed at the outputs of the pulse distributors 6 and 2O. Due to this, by the end of the cycle A, the CODE 1001 is recorded in all registers 7 of the peripheral devices 1. This code simultaneously via interface blocks 12 is fed to the input of the numeric conversion unit 13, where the numeric constant code equal to the difference between the numerical expressions is added to the numerical expression response and address codes common to all peripheral devices 1y (in this case, this constant is 1), as a result of which the output of this block to the register 14 receives the code 1010 (see Fig.2, d), i.e. the expected value of the code to be transmitted on the communication line in cycle B. By the end of the cycle, when the synphasing receive unit is allocated 4 peripheral devices 1 of the next in-phase sync that goes to the control codes of the address code 8 of these devices, the address code 8 decoders implemented analysis of the code recorded in registers 7, and at the output of the decoder of the address code of that peripheral device 1, the address code of which is the received code, a signal is generated that arrives at the control unit and 9. From the output of block 9, if there is no signal at the signal input 33 of this peripheral device 1, a signal is sent to the driver of the response code 10, after which this code is written to the register 7 via the inputs of the parallel recording 1010). At the same time, a signal is generated at the output of the control unit 9, unlocking the valve 11, 5478 which is then applied to the clock input register 7 of the next burst of pulses from the output of the pulse distributor 6 (see Fig. 2c), the response code is output within cycle B peripheral device 1 through the valve 11 to the communication line 3 (see Fig.2, g). The suppression of the break; the signal at the output of the control unit 9 is carried out after the next pulse from the output of the reception unit 4 is supplied to its control input. Thus, the duration of the open state of the partition 11 is one clock cycle. The code transferred to the communication line 3, as well as the previous one, is recorded in the registers 7 of all peripheral devices 1, after which, at the end of the clock cycle, it is analyzed using the address codes 8 and | Etc. At the same time, this code, as well as the previous one, enters the numerical conversion unit 13, at the output of which it is converted into code 1011, which arrives in time B at the input of register 14 (see Fig.2, d). In addition, code 1010 arrives in tact B. through an interface block 12 on a numerical input comparison unit 16, to another numeric one; The input of which receives the same code from the output of the register 14. Since the values of all bits of the codes that are postponed to the numerical inputs of the comparison block 16 coincide, no signals appear at its output. As a result, the control unit 17 is in a decelerated state and at its command outputs 29.31 and 32 permanently prohibitory signals are present, and the output of the AOR is resolving. Due to this, the code O1O within the cycle B is rewritten via valve 27 from register 14 to register 15 (see fkg.2, e). Thus, by the end of cycle B in register 15, there is a recorded code that must be transmitted in this cycle over communication line 3. During normal operation of all peripheral devices 1, no interruptions in communication line 3 and no signals at the inputs 33 peripheral devices 1, the operation of the device is carried out in the described manner up to the formation by the peripheral device 1 of a response code 1111 consisting of only single characters and not being. the address code of no other peripheral device 1. At the same time, no code signals are transmitted along the communication line, which is equivalent to the transmission of the LLC code, which is also formed by adding units to the code 1111, as a result of which the signal is received. The comparison block 16 in this cycle is also absent. If, in turn, the LLC code is the address code of one of the peripheral devices 1, the code generation circuit 3 is automatically restored and the device continues its operation. Thus, the process of polling all peripheral devices 1 included in the device consists in successive generation on the communication line only of the address codes of these devices, which reduces the information transmitted through the communication line to the achievable minimum. from a monitored object at input 33 of some kind of peripheral device 1 (indicating, for example, an emergency condition of this object), at the output 6noka of control 9 of this device after applying a signal from the output of the decipheror ad to it eo. code 8, an additional signal is generated, which arrives at the shaper of the response code 10 and causes distortion of this code. As a result, in the next cycle, instead of the response code, this peripheral device 1 outputs some other code to the communication line 3 (for example, code 01О1 instead of 1O11 code in cycle B (see Fig. 2, d). This code arrives through the interface unit 12 and a numeric code conversion unit 13 into a register 14 is converted into an IT code (see Fig. 2, d). At the same time, this code enters the comparison unit 16, which, from the output of register 14, enters the expected value of the code, t. e. code 1011. As a result, already at the first non-coinciding position of these codes, the comparison unit 16 A signal is sent to the start input of control 17 (see Fig. 2, g), after which, at the output 29 of this block, a resolution signal j arrives at the control input of valve 28 (see Fig. 2.3). In the same cycle, the code ixuj from register 14 through valve 27 is rewritten into register 15 (see Fig. 2, e), and the closest impulse from the output of the synphating pulse generator 19 through open valve 28 is fed to the starting input of the terminal conversion unit 21 ( cm. 2, and), carried out his preparation for receiving information. . The falling edge of the nearest pulse from the output of the sinus pulse generator 19 is switched by the control 17, after which the inhibit signal is restored at its output 29, the valve 28 is shuffled (see fig, 2, h), the inhibit signal appears at the PL output, which turns off the comparison unit 16 and a shut-off valve 27 (see fig, 2, and), and at output 31, an enabling signal occurs that unlocks the valves 23, 24 and 25 (see fig; 2, l). As a result, in cycle G, code 1101 {the response code of the peripheral device 1 that received an alarm on input 33) is transmitted through an open valve 23 to the terminator; transformation 21 (see Fig.2, m), and; at the same time through the open valve 24 is rewritten again to the register 15 (see FIG. 2, e), and to the communication line 3 via the interface block 12 and the open valve 25; from the source of the single signal 2, the code 1111 is received, consisting only of the individual ones characters (see Fig.2, g).

The latter is necessary in order to muffle the response code of the peripheral I device 1, for which it is distorted; the response code of the peripheral device that received the signal at input 33 is addressed.

. ;;, Since the comparator block 16 in the cycle G is turned off by the signal from the output 30 of the block; control 17 does not receive any signals from its output. The IT code in register 14 is replaced by the LLCO code (see Fig. 2, e), which is the result of the conversion of the 1111 code in the numerical conversion unit 13.

The terminal transform block 21 transforms the received code into a form necessary for further use (by the operator of the device or other recording or control devices).

The back edge of the pulse from the output of the synphating pulse generator 19, formed at the beginning of cycle D, is another connection of the control unit 17, after which at its output 31 the inhibit signal is restored, locking the gates 23,24 and 25, and at output 32 a slider appears signal, unlocking valve 26 (see f g, 2, and).

As a result, within the cycle D, in the communication line 3, via the interface unit 12 and the open valve 26, the code 1011 is entered from register 15 (see Fig. 2, d), i.e. : the one KOjOj that was used to answer the peripheral device 1, which received the

 eight

1 signal by input 33, if this signal were not.

This code, having passed through the numerical conversion unit 13, is written into the register 5 14 as the code 111 O (see Fig. 2, e.), I.e. in the form of the expected value of the code, which must be transmitted on link 3 in the next cycle.

The comparison unit 16 in the D cycle still does not generate any signals, due to the presence on its control input of the inhibit signal from the output 30 of the control unit 17 (see Fig. 2, k). The register 15 in tick D, due to the presence of the inhibit signals at the control inputs of the gates 24 and 27, is nullified (see Fig. 2, e) The code transmitted over the communication line in the tick D is recorded in the register 7 of all peripheral devices 1, and one of them is 20: it perceives it as an address and, in the next clock cycle, when there is no signal at its input 33, it generates its own;

The trailing edge of the pulse formed by 25 in the next cycle by the inhaling pulse former 19 is switched next by the control unit 17, after which the signals corresponding to its decelerated state are restored at all its inputs: see FIG. k, l, n), and the operation of the device is carried out in the manner already described, similar to the cycles A and B. i The devices operate in a mode similar to 35 cycles of C, D, and D also in | cases if any peripheral device 1 starts to generate a link communication response code is invalid as a result of failure, as well as at breakage line. 40 communication with any one or a group of peripheral devices 1. In any of these cases, information is output to the terminal 21 conversion unit identifying the number of the peripheral 45 device 1 in which the emergency situation occurred.

Subject invention

A system for tele-impinging with time division of signals, containing - peripheral devices, 1st of which are made on the distributor of impulses eg, whose inputs are connected respectively to the synphasing and synchronization receiving units and the output connected to the first input of the shift register, the first output

which, through the address code decoder, is connected to the first input of the control unit, to the second input of which the output of the synphase receiving unit is connected, to the third - the signal input of the device,

the first and second output of the control unit. through the shaper response code under; The key to the second input of the shift register

the third output is connected to the control input; A second valve with another input is connected to the second output of the shift register; the inputs of the synchronization receiving and synchronization units; the third input of the shift register and the output of the controlled valve are connected to a communication line connected to the receiver’s interface unit , an eye / non-transform unit, controlled vectors and a pulse distributor, the inputs of which are connected to the outputs of the common-mode and clock generator, the second output of which is connected to the input sinfaziruyushih pulse shaper and to the first row WMOs unit interface, the second input of which

connected to the output of the synformer. control pulses to the first input of the control unit and the first controlled valve, characterized in that

In order to increase the speed of polling the system, in it, in each peripheral device, the output of the syncating receiver is connected to the second inputs of the address code decoder and the control unit, and the second is inserted into the receiver.

a shift register, a comparison unit, a numerical conversion unit and a single signal source, the output of the interface unit connected to the first inputs of the comparison unit and the numerical conversion unit whose output through the first shift register is connected to the second input of the comparison unit and to the input of the second controlled valve whose other input is connected. to the third input of the comparison unit and the first output of the control unit, and the output to the first input of the second shift register, the second input of which is connected to the corresponding inputs of the first register shift n and the numerical conversion unit and the output of the pulse distributor, and the output to the first inputs of the third, fourth the second and the fifth controlled valves, the second inputs of the third and fourth controlled valves are connected to the second output of the control unit and to the input of the sixth, controlled valve, and the second input to the third output of the control unit and the control, the second input of which is connected to the reference LOCODE, and the fourth output, through the first controlled gate, is connected to the nepBtiM input of the terminal conversion unit, to the second input of which the third controlled gate is connected, the output of the fourth is connected to the first input of the second shift register, way out

and the sixth are combined and connected to the third input of the interface block, with the second J

. the input of the sixth controlled valve is connected to the source of a single signal. 3 I

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