SU503239A1 - Control device - Google Patents

Description

The software access to the processor's checked equipment and the analysis of the results of actions are carried out with the help of special diagnostic commands involving a small part of the processor's equipment (completely excluding the operating device).

FIG. 1 shows a block diagram of the described device; in fig. 2 - command register, represented by formats A, B and B.

The block diagram contains the command register 1, the micro-command address register 2, the micro-command memory 3, the micro-command register 4, the micro-command address modifier b, the logical conditions extraction node 6, the decoder for comparison with zero 7, the decoder for installation 8, the interrogator for polling 9, the installation switch 10 , the polling switch li, the allocation node of the controlled bits 12, the address highway 13 and the information highway 14.

Bus 15 receives a command code from a memory. Bus 16 corresponds to the issuance of the address of the teams. The bus 17 carries the logical conditions generated by the processor ' device. The micro-command address modifier 6 stores the branch condition and forms the address of the next micro-command. The allocation unit 12 allows the formation of a branch condition depending on the state of the bits being monitored (for example, the size of the fault register, logical conditions, etc.). The type of controlled bit is given by the mask code in field 18 of the instruction register. The command register field 19 contains the operation code (CCP) of the current command. Field 20 sets the address of the memory elements (AEL), which is decoded by the decoder 8 in the case of an installation operation and decoder 9 in the case of a polling operation. In the register field 21, a verification code and a reference code are specified in the case of an installation and polling operation, respectively. The installation of the verification code in the memory elements is carried out with the help of the switch of installation 10, and their status is polled with the help of the interrogator switch I. code with accepted. The zero-decoder 7 determines the result of the polling operation by which the branch condition is formed.

The command register is represented by two formats B and B.

The operation of the device in the execution mode of conventional computing programs does not differ from the operation of known devices.

In diagnostic mode, the processor is controlled using special diagnostic commands: "Installation,." Poll, "Analysis," Branching. All of these commands, except for the specific part that determines the specifics of their work, have a standard part associated with sampling the next command from the storage device. The Installation and Polling commands have the format B. The specific part of the Installation command includes one micro-command, and the commands Poll are two micro-commands. The command “Analysis has format B and the concrete part consists of one micro-command. The branch command, which performs the transition — by the condition of branching, has the format A and practically does not differ from the usual conditional transition commands.

Claims (1)

Invention Formula A control device comprising a command register, a micro-command address register, a micro-command memory, a micro-command register, a micro-command address modifier, a logical conditions selection node, the first input and the first output of the command register are connected to the first input and output of the device, respectively, the second command output connected to the first input of the micro-command address register, the second input of which is connected to the output of the micro-command address modifier, and the output through the micro-command memory is connected to the input of the micro-command register, The first output of which is connected to the first input of the micro-command address modifier, the second input of which is connected to the output of the logical conditions allocation node, the first input of which is connected to the second output of the micro-instructions register, and the second input is connected to the second input of the device, characterized in that equipment in the diagnostic mode, it contains three decoders, two switches, a node for the allocation of controlled bits, an address and information lines, the third and fourth outputs of the command register through the node the allocation of controlled bits and the first decoder are respectively connected to the third and fourth inputs of the microinstruction address modifier; the fifth, sixth and seventh outputs of the command register are connected respectively to the inputs of the second and third decoders and the first switch; the output of the micro-register register is connected to the control inputs of the second decoder and the first switch, and the fourth output of the micro-register register is connected to the control inputs third of the decoder and the second switch, the output of the second and third descriptors are connected to the address trunk, and the output of the first and input of the second switch are connected to the information highway.