SU478338A1 - Device for recording information - Google Patents

Description

(54) DEVICE FOR REGISTRATION OF INFORMATION

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The image relates to automation and computer technology and can be used as an external device of an information-measuring system for outputting and recording alphanumeric information.

Information recording devices are known that contain memory registers connected to each other, a sweep clock generator, a receive register, a code distributor associated with an ele- ment, a delay cop, and through sequentially connected and divided into groups of circuits: comparisons, circuits, and drivers - with recording electrode recording electrodes, character code driver, CBS | stoner with receiver register, sweep generator, memory registers, reference circuits, driver and synchronization units, connected and groups through AND gates and decoders cycles zapisiso counters recording cycles connected to each other and to a generator recording cycles.

The proposed device is different from

known to contain an overflow counter, a matching circuit and triggers controlling the beginning and end of the recording of the printed line, the overflow counter being connected to the write clock counters, the matching circuit associated with the delay element and one of the counters such as that to the element delays and trigger control & laziness of the start of recording the printed, string associated with the recording clock counter and one of the decoders of the recording cycles, are connected via a trigger controlling the end of the recording of the printed line with another tact decoder for recording and recording clock counter.

This allows improving the quality of recording information, reducing the amount of equipment in the device.

The drawing shows a block diagram of the proposed device.

The device contains a sweep generator 1, a receive register 2, a code distributor 3, memory registers 4, comparison circuits 5, a symbol code generator 6, AND 7 circuits, drivers & a write clock generator 9, an overflow counter 3 10, a matching circuit , delay element 12, write clock counter 13, trigger control the end of the recording of the printed line 14, write clock counter 15, trigger control of the recording of the printed line 16, de write clock encoders 17 and 1 synchronization blocks 19, recording device 20. The device is working following about time, the input information in the form of parallel binary coded decimal code is supplied to the receiving register 2, which is converted from parallel to serial. The advancement of information from the receiving register-2 to the registers of memory 4 drying is a pulse coming from the gene & Sweep clock 1, As they arrive, the converted digital code is sequentially distributed by code allocator 3 to memory 4 registers 4, The capacity of each memory register is equal to the capacity of the receiving register, and the number of receiving registers to the number of registered groups in the printed line. The code distributor 3 performs the switching of groups by clock pulses, the frequency of which corresponds to the frequency of changing the code of digital information. The decoding of the contents of memory registers 4 is performed by comparison circuits 5 The character code generator 6 generates a cyclically varying interrogation code. This code is fed to circuits for comparison with codes stored in memory registers. When the two codes match at the outputs of the comparison circuits 5, a digital signal is generated. The phase of the pulses at the output of each such circuit is proportional to the digital code of each decimal digit of the register. The frequency of interrogation of a code received is much greater. The frequency of changing digital information in memory is 4 memory, in order to repeatedly poll these registers. The storage time of information in each memory register is greater than Kim equal to the time for extracting a group of characters to a paper tape. Synchronously with the polling, the symbol code generator generates a scan signal. Sequences of all the symbol sweep signals are sent to the blocks of the formers 8, at which subdivision signals from the outputs of the And 7 circuits select the codes for registering the symbols stored in the memory registers 4 Since the frequency of the sweeps of the character code exceeds the frequency of extracting the symbols , the device has a generator of recording cycles 9 and clock synchronization 19, the generator of recording cycles 9 generates pulses with a frequency proportional to the speed of movement of the recording reader, and this frequency is equal to the greatest hour OTE input information and provides a printed record of parallel-line post-: successive manner with its smallest inclination At frequencies mengsche input information for limiting frequency of the recording apparatus when recording information observed increase printing line tilt, which is in inverse proportion to the frequency of the input code. To keep the printed line tilted constant, the overflow counter, U, determines the time taken for the existing fill cycle — the memory registers (for the limit frequency) over the main (for the limit frequency) and delays the recording of the line by a time equal to the excess of the cycle over the main one. The formation of recording cycles is as follows. The signal from the first output of the distributor of codes 3 selected after the beginning of the cycle of filling the memory registers 4 through the electric amp, delay 12 sets the overflow counter 10 to the zero state and controls the beginning of the printed line 16. In the Ha4ajTbHOM state, this trigger generates a signal the bar arriving at the decoder of the recording cycles 18. The overflow counter 1O calculates the main cycle and, prior to the arrival of the next reset pulse, counts the excess of the current cycle over the main one. At the next excitation of the same distributor bus, a pair of OO occurs (} the transfer of the reverse cycle cycle excess code from the overflow counter 1O to the counting clock counter 15 through the matching circuit 11 occurs. From the moment the cycle starts, the counting counter also calculates the delay time the zero state overturns the trigger to control the start of the recording of the printed line 16, thereby giving the permission signal to the decryptor of the recording cycles 18. In this case, the period of formation of a half of the recording cycles is performed. In the last bus of the write decoder 18, the end-of-record control trigger of the printed line 14 overturns and sends a enable signal to the count of the write clock counter 13 and to the write decoder 17.

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With this phase, the second half of the write cycles is formed, after which the clock counter 13 by the recording end signal overturns the control trigger 14, which prohibits the signals from entering the counting input of the counter 13 and the decryptor 17 to the next enable signal from the output of the write decoder 18. the write cycle is repeated. The operation of the tick counters in one cycle may overlap, and with the input input frequency equal to the limiting frequency for a given speed of carrier sweeping, it is performed in parallel.

Synchronization blocks 19 are used to allocate write cycles to groups, each of which records one register information and fills them with symbol sweep cycles. At the outputs of sync blocks 19, each of the character write cycles is a corresponding group of sweep pulses. The first recording cycle consists of a group of pulses of the first symbol sweeps, the second recording cycle — from a group of pulses of the second clock p of the sweep, and so on.

Bundles of sweep pulses are followed sequentially in the order they are written

decomposition fragments. From the stack of sweep cycles for each decimal bit, circuits And 7 allocate clock ticks to the pulses of the comparison circuits 5. The control signal generated in this way on the blocks of the driver 8 samples the sequence of the symbol sweep codes of the code that corresponds to the input digital code. Sampling the fragment} 1t registration due to the recording cycles occurs with a partial thinning corresponding to the recording time. Control device

consistently includes elements of the recording unit of the recording device 20 and makes it possible to obtain a set of prints, for example, on paper, in the form of alphanumeric text.

Subject invention

A device for registering information containing parallel connected memory registers that are connected to a sweep generator, a receiving register, a code distributor associated with a delay element, and through sequentially connected groups of comparison circuits, And circuits and drivers, with food-sensing electrodes of a recording unit, a symbol code generator associated with a receive register, a sweep clock generator, memory registers by reference circuits, shapers, and synchronization blocks connected to The corresponding groups of the AND circuits and through the decoders of the recording cycles — with the counters of the {recordings connected with each other and with the generator of the recording cycles, characterized in that, in order to improve the quality of recording and simplify the device, it contains an overflow counter, a coincidence circuit and triggers controlling the beginning and end of the recording of the printed line, the overflow counter being connected to the write clock counters, the matching circuit associated with the delay elements and one of the write clock counters, the delay element and the trigger y the start of recording of the printed line associated with the write clock counter and one of the decoders of the write cycles, connected via the trigger to control the end of the recording of the printed line with the other decoder of the recording cycles, and the counter of the write cycles.

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