SU466499A1 - Digital frequency synthesizer - Google Patents

Description

The invention relates to specialized computing hardware and can be used in particular for speech synthesis, for generating weighting functions in adapting digital filters, for synthesizing sipnal, intended for diagnostics and tuning of the gf spectral analyzers.

A digital device is known that allows to synthesize a frequency spectrum from eight frequencies by means of weighting | Vani amplitude discrete harmonics containing the amplitude memory block, the address counter of the memory block, the adder and the digit converter - analog.

However, in such a device, the number of simultaneously used frequencies for signal synthesis is limited.

The purpose of the invention is to improve the accuracy of the device.

This goal is achieved by adding an additional counter and adder to the device, the input of which is connected to the output of the additional counter, the input of which is connected to one of the inputs of the main and additional adders, another input of the additional adder is connected to the address counter and two valve circuits. The inputs of the first valve circuit are connected respectively to the output of the additional adder, the main som.mator input and one of the inputs of the second valve circuit, the other inputs of which are connected to the output of the additional adder i of the amplitude memory, the input of which is connected to the output of the address counter. The inputs of the matrix multiplication unit are connected to the outputs of the valve circuits, the input of the memory register is connected to the output of the matrix multiplication unit, and the output is connected to the input of the main adder, the output of which is connected to the nifra analogue converter. The sign output of the additional counter is connected to the same input of the additional adder, the sign output of which is connected to the sign bit and one of the inputs of the main adder.

The drawing shows struktktAn diagram of the generator.

The generator consists of a counting device, a discrete number}, accumulator sum.mator 2, gate circuit 3, matrix multiplication device 4, gate circuit 5, memory register 6, accumulator sum 7, address counter 8, storage unit 9, transducer. - a.alog / 0.

The discrete values of the sinusoids are calculated by the formula:

(-1) ta / g (M-tp) ss A,

3

where rt 0,1,2 ... is the current number of the generated samples; (Of, with ,, is the reduced frequency;

T is the period of arrival of counting pulses;

T 1,2,3 ... M - the number of the generated frequency;

1 8.I- “

/ 1 - ,, - scale factor

 tp

l is the whole part of the ratio,

TP TP - CL1 The device implements the algorithm

y „- 2 (-) /“ “-W / n / g).

where b, „- am.llydduy gth garmo; shki.

The principle of operation of the device is as follows.

The counter / number number of the event during the period of receipt of the counting pulses I M is added IB accumulating adder 2 times with summing pulses II. In the numerical line of the adder, the values of tp-tp-kM are formed successively for the period of receipt of the counting pulses 1. The forward and reverse codes of these quantities, respectively, through valve circuits 5 and 5, which are affected by (pulses III), are sent to the matrix multiplier 4. The result of multiplication mn i (M - mn) is written by the V-pulses into memory register 6. Next, and post1pleni1I | And and: mpulso: in IV-on the fan circuits 3 and 5 "and multiplied multiply by the m-attribute multiplier) The resulting m-th count of the m-th sinusoid on the W-amplitude of the n-th frequency, which comes from memory block 9. The result is pulsed V is recorded. In memory register 6 and pulse VI is added to the drip ivayuschy adder 7. The adder 7 Control (Addition - Subtraction) vedets from the sign bit of the accumulator 2. The state of the address counter 8 memory varies pulses P. After summing M

of such cycles, the result is read from the accumulating adder 7 by pulses VII. With the arrival of the next reporting pulse I, zeroing of adders 2 and 7 is performed.

In the process of operation in the accumulating adder 7 successively formed H ((S

.U

2dl - 1) (- and- - “)

representing the discrete values of the synthesized signal. A continuous value of the signal after r (can be obtained; the pinch of the pinch is analogous to W.

Subject invention

A digital frequency synthesizer containing an amplitude memory block, a memory block address counter, an adder and a pres / brazo, a digit is an analogue characterized in that, in order to improve the accuracy of the device, it includes

counters, and adder, the input of which is connected to an additional counter, whose input is connected to one of the inputs of the main and additional adders, another input of the additional adder is connected to the address counter, two valve circuits, the inputs of the first valve circuit are connected respectively to the output of the additional adder, the main adder and one of the inputs of the second ventilation circuit, the other inputs of which are connected to the output of the additional adder and the memory storage unit, the input of which is connected to The output of the address counter, the matrix multiplication unit, whose inputs are connected iC outputs of valve circuits, real-JCTip there pi, the input of which is connected to the OUTPUT.M matrix unit is decoded, and the output - with the input of the main sum-ator, the output of which is IK converted (to the recipient, the figure is an analogue; moreover, the sign output of the additional counter is connected to the inputs of the additional and main adders of the same name and to one of the inputs of the main adder.