SU734706A1 - Digital synthesizer for scanning combinations - Google Patents

Description

The invention relates to specialized computational technology tools and can be used in digital special analyzers of parallel action, in speech synthesizers, in generators of the weight functions of adaptive digital filters. A digital sine-cosine function generator is known, comprising a counter, a memory, an adder, and And i. However, it has a large error (4%) and low speed. The closest to the technical essence of the present invention is a synthesizer containing the first counter connected to the first input of the accumulator A new adder connected to the first input of the first gate circuit connected to one of the inputs of the matrix multiplication unit, the other input of which connected to the output of the second valve circuit, the first input of which is connected to the inverse of the adder, the output of the multiplication unit is connected to the output of the first memory register 23. The device indicated, had a high IMM fast The action, when generating sine-indirect signals, has low accuracy. The purpose of the invention is to improve accuracy. The goal is achieved by the fact that in a synthesizer containing the first counter, the output of which is connected to the first input of the adder, the direct output of which is connected to the first input and the inputs of the AND elements of the first group, the outputs of the AND elements of the first group are connected to the first input of the multiplier multiplexer, the second the input of which is connected to the outputs of the elements AND of the second group, the first inputs of which are connected to the idle output of the adder, the output of the matrix multiplication unit is connected to the input of the first memory register, the second counter, the second and t are entered These memory registers, the output of the second counter is connected to the second inputs of elements AND of the second group, the output of the first memory register is connected to the second inputs of epeeitis AND of the first group and adder, the output of the matrix multiplication unit is connected to the third input of the adder and the first inputs of the second and the third memory registers, the second inputs of which are connected to the direct output of the adder, and the outputs respectively to the fourth and fifth inputs of the adder, the direct output of which is connected to the output of the synthesizer.

FIG. 1 shows the block-: heme synthesizer; in fig. 2 - time diagram of its digital pulses.

The synthesizer includes counters 1, 2, adder 3, groups of elements 4, 5 AND, matrix multiplication unit 6, registers 7-9 of memory.

The generation is carried out along the lines.

V. - 0 (; (-) i (M-vmn sKstnmuj r

(

Q. (-. FC,) |: M- (

lsos.55

(

 KsovtSdP,

de p Oh, 1, 2, .... - current number

crates generated is the basic frequency; T is the period of quantization of the harmonic signal;

And - the capacity of the numerical line accumulating adder; Gg is the number of the generated frequency

2 you (max m-M); - scale factor} Y-, (coefficients "you are equal to:

 a, - V27; c / lg.z;

, Gtlp1 ...

K.

J imn

1m j

g-ep11 (mn.-Omn.) - e.M

/ Vc

(-) - discrete sine wave sign

rsignal,

(Y I is the cosine signal.

The first terms of the right-hand sides of expressions (1) and (2) approximate, with an accuracy of up to 4%, the discrete values of the sine-wave and cosine-wave signal of frequency m {jij according to the following expressions

(-) mn {M-mnyAsinmuj n-vM -g / z (

to sin (З-Я, т и / ДП,

(3)

((T (mn -) M- (i V) Acostn pt V.

The approximation error is determined by the presence in the form of the odd harmonics of the frequency ilnujQ formed by P. The largest error components form the 3- and 5-harmonics included in the sums of expressions (3, 4) with coefficients 1/27 and 1/125, respectively. . Algorithm 1 (or 2) for calculating the reference of a sinusoidal (or cosine-shaped) signal with methodical error I 4 0.6% includes, along with the calculation of the main result 3 (or 4) and the calculation of the 3rd and 5th successor of the frequency hp uj Q and also subtracting them, respectively, with weights 1/27 and 1/128 from product 3 (or 4).

Works digital synthesizer as follows. The number of the produced frequency m of the scsusoidal signal is set in the counter 2 by control pulses 1 (Fig. 2). At the same time, the current sampling number of the signals n is set in the counter 1 by pulses Y 2, and then by pulses V 3 is recorded along the corresponding circuit into accumulating adder 3. After this, the high-speed matrix multiplier is used to calculate the product G T with supplying potential values V 10 to the elements And 4, 5. After the time required for multiplication, the product trm is written into register 9 with V 16 pulses, then rewritten into adder 3 along the recording circuit with V pulses 4. Forward code mh and reverse PM-multiply are fed to a multiplier with potentials tsialnshh pulses have 11 to respective input gates. The result of multiplication, equal to the first term-relation of expression (1), is recorded for storage in register 8 by pulses V 14 (Fig. 2).

Claims (2)

After that, in the accumulating adder, the value mn is added twice with register 9 pulses V 5 and the same value stored there, i.e. a phase 3 harmonic is formed - 3 pt. Then, in the multiplier, the product of the direct and operational code of this phase is calculated, i.e. The count of the 3rd harmonic of the sinusoidal signal is formed and, after its formation, is recorded in register 7 with pulses of V 13. At the same multiplier, the third harmonic signal of the 3rd harmonic signal coming from register 7 is weighed through the input gates 4 with the help of potential pulses. V 12 The value of 1/27 enters the second multiplier beam from elements 5 And using the same pulses V 12. At the same time, a phase 5 harmonic of 5 gpc is formed in the accumulating adder by doubling the stored accumulator to the stored sum. The result of the tp value on register 9 is generated using summation pulses V 5. The resulting value of 5 frm is written to register 9 by pulses of V 17. After this, the value described by expression (3) from register 8 is added to the adder 3 and the BiBaeTCH register (8). ) by the time educated in the multiplier. Then, the result is written to register 8, and to accumulating adder - the value 5 from register 9 by pulses V 4. After that, the multiplier calculates the 5th harmonic, which, after its formation, is output to register 7c with a weight of 1/128. Weighing 5 samples of the harmonic is done by shifting the bits toward the older one when overwriting from the duplicating device to the register 7 pulses V 18. At the same time, the accumulator admits V 8 pulses from the register 8 to the first right difference of the expression. (1), from which the weighted count of the 5th harmonic stored in register 7 is then subtracted, using pulses V 9. 9. The result obtained nsin formed with an error of not more than 0.6-o is output to the accumulator 3 accumulator. receiving and the cosine sirnal of the same frequency, the calculation procedure is repeated with the only difference that each time after the formation at the current time point in the adder (3) the value of gpc, it is increased by m / 2 by adding one to the most significant digit of the adder The V 8. 7 impulse pulse 66 shows a short time diagram, the duration of the calculation of both sine and cosine samples is determined by the execution time of 6 multiplication operations on a matrix multiplier maybe high. Hence the speed of the generator is quite high. This device with the help of an additional counter, two additional registers and a new organi- zation of communications allows flexible mujQ frequency tuning and generates countings. Sine-wave and cosine-sag o, along with any of muj frequencies (ja error of not more than 0, 6% DETAILED DESCRIPTION OF THE INVENTION A digital synthesizer of an imyco sinusoidal signal with a first counter, the output of which is connected to the first input of a accumulating adder, the direct output of which is connected to the first inputs of the elements of the first group, b. The first element of the first group is connected to the first input of the matrix multiplication unit, the second input of which is connected to the outputs of the second group elements, the first inputs of which are connected to (the slotted sum of the torus, the output of the matrix block at the base is connected to the input of the first memory register, which differs , 4TOj with the aim of increasing accuracy, the second counter, the second and third memory registers are entered into the disinser, the output of the second counter is connected to the second inputs of elements AND of the second group, the output of the first memory register is connected to the second The inputs of the elements of the first group and the adder, the output of the matrix multiplication unit are connected to the third input of the adder and the first inputs of the second in the third memory registers, the second inputs of which are connected to the forward output of the adder, and the outputs The inputs of the adder, the direct output of which is connected to the output of the synthesizer. Sources of information taken into account during the examination 1. USSR author's certificate No. 399851, cl. Q 06 F 1/02, 1971. 2. USSR author's certificate k 466499, cl. G 06 F 1/02, 1974.