SU444191A1 - Multichannel Correlometer - Google Patents

Description

one

The invention relates to a correlation analysis and can be used in automatic control and information processing systems.

A multi-channel correlometer is known, which contains a module allocation circuit, a control unit, a switch, a block of analysis levels, a comparison circuit, a centering filter, an analog-to-digital converter, channel AND patterns, an OR circuit, a time selector, a sample number counter, and reversible totalizers.

However, the known correlometer is suitable.

only for the analysis of Gaussian processes.

The aim of the invention is to expand the class of processes under investigation.

For this, the correlometer contains comparison circuits, an address block, two keys and voltage dividers, the inputs of the OR circuit are connected to the outputs of the delay block, and the output is connected to the first control inputs of the keys connected via voltage dividers with the corresponding inputs of the analog-digital converter; information inputs of keys are connected to the output

the home of the module allocation circuit, the second control inputs of the keys are connected to the corresponding outputs of the address block, the other two outputs of which are connected respectively to the inputs of the first and second channel circuits AND; the inputs of the address block are connected to the allocation circuit of the module, to the output of the delay block and to the outputs of the comparison circuits that are connected to the time selector; The first inputs of the comparison circuits are connected to the centering filter, and the second - to the corresponding outputs a block of analysis levels.

The invention is illustrated in the drawing.

The drawing shows a block diagram of a correlometer.

The multichannel correlometer contains a centering filter 1, comparison schemes 2-1 to 2-4, block of analysis levels 3, block of address 4, allocation circuit of module 5, keys 6-1, 6-2, control block 7, time selector 8, generator counting pulses 9, delay block 10, OR circuit 1 I voltage dividers 12-1, 12-2, analog 1, digital converter 13, AND circuits 14-1 to 14-1 summing inputs of summators 16, circuits AND 15-1 to 15G subtracting inputs of adders 16, reversible adders 16-1 - 16-С. , the number of samples counter 17, the switch of the type of work 18, the autocorrelation function is determined at position 19, and the cross-correlation function, the Start button 21, at position 20,. The correlometer works as follows. Let the number of levels of analysis be f 5, and switch 18 be in position 20, Implementing a random process XCt) from input 1 pass through a centering filter 1. And enter the first inputs of the comparison circuits, i to the second inputs of which from the outputs of the level block, analysis 3 The corresponding values of the constant voltage levels X are supplied. The implementation of the random process Y (t) through the type of work switch 18 enters the address block 4 and through the allocation circuit of module 5 to the information inputs of keys 6-1 and 6-2. When the Start button 21 is pressed, the control unit 7 generates a series of control pulses and the initial state of all the functional blocks is set. In MOMeHTt - the equalities X (t) :: X, one of the comparison circuits 2-1 triggers, for example, when x (.t) -X2, the circuit 2-2 works. The comparison pulse opens the time selector 8 to pass a sequence of counting pulses from the generator 9 to the input of the block 1O. The latter generates polling pulses with a repetition interval dT and distributes them to p parallel channels (1 is the number of ordinates of the correlation function). The comparison pulse from the 2- {scheme is fed to the address block 4, in which the L number of the triggered comparison scheme is stored for the maximum delay time Gg G-dT, in our example it is the 2-2 circuit. The resolving potential from the address 4 block at the same time is fed to the second control input of the key 6-1, if x (t) XiVXi, or the key 6-2, if xCt) X2VX, j, which is the case in our example. The first pulse from the delay unit 10 passes the OR 11 circuit, opens one of the first control inputs, one 6-1 or 6-2 (in our example, the key 6-2), at the output of which appears im-. pulse with amplitude equal to the module of realization of the random process YU) at the moment of time t. This impulse through a voltage divider 12-1 or 12-2 enters an analog-digital converter 13, where its amplitude is converted into a number-pulse code. When the signs of the analysis level X coincide, and the implementation value y (t) from the address block 4, the resolution signal arrives at the AND 14-1 circuit, if the characters do not match, the resolution signal arrives at the AND 15-1 circuit and pulses from the ADC pass into the reversible adder 16-1, respectively, either through a summing or through a subtracting input. After a time d, a second pulse appears from the delay block 1O, which, having passed the OR 11 circuit, opens the key 6-1 or 6-2 (in our example 6-2) and a similar conversion to the pulse number code of the realization value y ( t + dT), which is written to the reversible adder 16-2. After the conversion of the implementation of Y (LT. I, the work cycle is completed, the unit is counted in the count of samples 17 and the initial block of address block 4 and time selector 8 is set. The next cycle starts when X (t) compares again with one of the X levels When counter 17 overflows, the operation of the correlometer ends and the numbers proportional to the ordinates of the estimate of the mutual correlation function of the processes (1) and YCt will be written in the reversible adders 16-1-1p-P. The subject of the invention. A multi-channel correlometer containing a module allocation circuit, a control unit, a switch, a block of analysis levels, an OR circuit, a centering filter, and an analog-to-digital converter connected to one of the inputs of each of the two channel schemes And, the second inputs of which are connected to the corresponding outputs of the block delays, one of the outputs of which is connected to the time selector directly and draws a counter of the number of samples; the outputs of the channel circuits AND are connected respectively to the summing and subtracting inputs of the reverse overt adders, characterized in that, with

the purpose of expanding the class of the processes under study, it contains comparison schemes, an address block, two keys and voltage dividers; the inputs of the OR circuit are connected to the outputs of the delay unit, and the output is connected to the first control inputs of the keys connected via voltage dividers to the corresponding inputs of the analog-to-digital converter; the information inputs of the keys are connected to the output of the module's circuit, the Bj-opbie control inputs of the keys are connected to the corresponding outputs of the address block, the other two outputs of which are connected to the inputs of the first and second channel circuits, the inputs of the address block are connected to the module's output circuit, to the output of the delay block and with the outputs of the comparison circuits that are connected to the time selector; the first inputs of the comparison circuits are connected to the centering filter, and the second to the corresponding outputs of the block of analysis levels.

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