SU432501A1 - DEVICE FOR THE FORMATION OF SIGNAL OPERATIONS - Google Patents

Description

one

The invention relates to the field of computer technology and is intended for use in digital computers operating with commands of various formats, in which the nature of the necessary actions is indicated either by ordinary half-bit ones. either pepalon relative (with a constant or variable base), either incomplete truncated opcodes, or, finally, codes of specific chains of sequentially performed operations — generic opcodes.

Devices are known in which, in addition to the command register, the decoder operation code and the switch, the device for generating operation signals includes a block of operation codes (micro-operations). This allows 01 erirovat with commands in which one initial operation code is indicated, and the subsequent operation codes are generated using the memory of the operation codes. However, such devices cannot generate opcodes using either full relative or “truncated opcodes,” as well as generic opcode codes. The use of command formats containing several relative or “truncated opcodes or generalized opcodes increases speed and spreads

the functionality of a digital computer by reducing the total time for requesting program information while simultaneously increasing the information capacity of the latter.

In order to increase speed and distribute functionality, a truncated opcode decider has been introduced into the device for generating operation signals; descrambler generalized opcode; length decoder; register of the base opcode; adder; counter; operation code driver and two communication units. The scheme of the device is presented in the drawing.

It consists of: inputs 1-8 and one output 9; command register 10, switch 11, decoder truncated operation code 12, driver of operation code 13, adder 14, first communication unit 15, register of basic operation code

16, the second communication unit 17, a depotfirator of the generalized operation code 18, a counter 19, a decoder of duration 20, a block of memory of operation codes 21, a register of operation code 22, a decoder of operation code 23.

Control inputs are fed to inputs 1-8, and the output of device 9 produces a signal for the corresponding operation.

The code of the next command is recorded in the command register 10. To perform each specific operation, the device generates a corresponding full-digit onerization code and writes it to register 22. This code is decoded by the decoder 23 and the output 9 of the device is given as a signal of the corresponding operation. The formation of a polydigit operation code on the operation code register 22 is performed differently.

Full-digit operation codes under the influence of control signals at input 1 of the device from the register of comaids 10 through the switch 11 and adder 14 are received through the first communication unit 15 pa register 22 under the influence of the control signal at the input 6 of the device and the register of the basic operation code 16 under the influence of the control signal at the input 7 of the device.

The truncated operation codes under the influence of the control signals on the input 2 of the device from the command register 10 through the switch 11 are sent to the decoder of the truncated opcode 12, the node by the influence of signals at the output of which the imaging unit of the opcode 13 generates the full-digit codes of the corresponding operations and writes them into the opcode register 22

The relative operation codes under the influence of the control signals at the input 3 of the device from the command register 10 through the switch 11 are fed to the second input of the adder 14, the first input of which is influenced by the control signal at the input 8 of the device from the register of the basic operation code 16 through the second communication unit basic operation codes are given. The full-digit operation code generated at the output of the adder 14 under the influence of the control signal at the device input 6 is fed to the register 22 via the first communication unit 15. In the case of a variable base, the same code under the influence of the control signal at the device input 7 from the output of the adder 14 through the first communication unit is entered in the register of the basic operation code 16.

The generalized operation codes under the influence of the control signals at the input 4 of the device from the command register 10 through the switch 11 are fed to the resolver of the generalized operation code 18. The decoder 18 outputs the control signal to the first input of the memory of operation codes 21 and prepares it for delivery to the register 22 sequences (chains) of full-size opcodes. At the same time, this compensation signal, which arrives at the first input of the counter 19, is prepared for the counting up to the value k, where k is the number of transactions encrypted with the generalized operation code. The contents of counter 19 are decoded by a decoder of duration 20. Under the influence of a signal on the excited bus of the decoder p, letter 20, arriving at the second input of the memory block of operation codes 21, and a signal from the output of the decoder of the generalized operation code 18, arriving at the first input of block 21, the latter issues full operation code per operation code register 22.

According to the signal of the end of this operation, which comes from the input 5 of the device, the contents of the counter 19 change, causing the next bus to be excited at the output of the decoder 20. The signal generated at this

the excited bus of the decoder of duration 20, provides for the issuance of the next full-size opcode of this chain from the block 21 of the opcode memory to the register 22 of the opcode. The process is repeated

until the input 5 of the device receives an A-oh operation termination signal.

Subject invention

A device for generating operation signals, containing blocks of operation codes, command register, operation code register, the output of which is connected to the output of the device through the decoder of the operation code, switch, characterized in that, in order to improve the speed and functionality of the device, entered the decoder truncated opcode, the decoder generalized opcode,

a length decoder, a base onerration code register, an adder, a counter, an operation code generator and two communication units; the four inputs of the device are connected to the same inputs of the switch, the fifth input of which is connected to the output of the register of commands, the first output of the switch through the serially connected defacertor of a truncated code operations and the operation code generator is connected to the nerve input of the code register

an operation, the second input of which is connected to the nerve output of the nerve communication unit, the second output of which is connected to the first input through the serially connected register of the base operation code and the second communication unit

adder, the second input of which is connected to the second output of the switch, the third output of which is connected to the input of the decoder of the generalized operation code, the output of which is connected to the first input of the memory block of operation codes and the first input of the counter, the second input of which is connected to the fifth input of the device, the output of the counter through the length decoder is connected to the second input of the memory block of operation codes, the output of which

connected to the third input of the operation code register, the output of the adder is connected to the first input of the first communication unit, the second and third inputs of which are connected respectively to the sixth and seventh inputs of the device, the eighth input of which is connected to the input of the second communication unit.