SU410392A1 - - Google Patents

Info

Publication number
SU410392A1
SU410392A1 SU1703792A SU1703792A SU410392A1 SU 410392 A1 SU410392 A1 SU 410392A1 SU 1703792 A SU1703792 A SU 1703792A SU 1703792 A SU1703792 A SU 1703792A SU 410392 A1 SU410392 A1 SU 410392A1
Authority
SU
USSR - Soviet Union
Prior art keywords
information
unit
address
bnb
cell
Prior art date
Application number
SU1703792A
Other languages
English (en)
Russian (ru)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to SU1703792A priority Critical patent/SU410392A1/ru
Application granted granted Critical
Publication of SU410392A1 publication Critical patent/SU410392A1/ru

Links

Landscapes

  • Data Exchanges In Wide-Area Networks (AREA)
SU1703792A 1971-09-28 1971-09-28 SU410392A1 (cg-RX-API-DMAC7.html)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SU1703792A SU410392A1 (cg-RX-API-DMAC7.html) 1971-09-28 1971-09-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU1703792A SU410392A1 (cg-RX-API-DMAC7.html) 1971-09-28 1971-09-28

Publications (1)

Publication Number Publication Date
SU410392A1 true SU410392A1 (cg-RX-API-DMAC7.html) 1974-01-05

Family

ID=20489860

Family Applications (1)

Application Number Title Priority Date Filing Date
SU1703792A SU410392A1 (cg-RX-API-DMAC7.html) 1971-09-28 1971-09-28

Country Status (1)

Country Link
SU (1) SU410392A1 (cg-RX-API-DMAC7.html)

Similar Documents

Publication Publication Date Title
US4008462A (en) Plural control memory system with multiple micro instruction readout
US3699533A (en) Memory system including buffer memories
US3292153A (en) Memory system
US3771142A (en) Digital data storage system
US4740923A (en) Memory circuit and method of controlling the same
JPH01500377A (ja) 2個のシステムクロックサイクルを利用する書込み動作をもったキャッシュメモリユニットを供与する装置及び方法
KR850004673A (ko) 디지탈 콤퓨터 시스템
SU650526A3 (ru) Устройство дл уплотнени каналов св зи
HU176777B (en) Device for reducing instruction execution time in computer of indirect addressed data memory
US3387272A (en) Content addressable memory system using address transformation circuits
GB1097909A (en) Data processing apparatus
US4561071A (en) Storage system having buffer storage
GB1406312A (en) Memory device
US3017094A (en) Order control arrangements for electronic digital computers
SU1472909A1 (ru) Запоминающее устройство с динамической адресацией
JPH0315772B2 (cg-RX-API-DMAC7.html)
JPS60186964A (ja) ベクトル処理装置
GB851418A (en) Improvements relating to digital computers
SU600926A1 (ru) Устройство дл записи информации
SU1065886A1 (ru) Динамическое запоминающее устройство
JPS5533282A (en) Buffer control system
SU407395A1 (cg-RX-API-DMAC7.html)
SU1075311A1 (ru) Устройство управлени дл доменной пам ти
SU864336A1 (ru) Логическое запоминающее устройство
SU455343A1 (ru) Уравл ющий автомат