SU402868A1 - SYNCHRONIZER OF THE INCLUSION OF FRICTION AND CAM CLUTCH - Google Patents

Description

one

This invention relates to the field of automation.

A known synchronizer circuit comprising two impeller drivers, the outputs of which are connected respectively to the first and second inputs of the switching unit, the outputs of which are connected respectively to the first and second inputs of the reversing counter, to the third input of which, through a differentiating amplifier, connect the first output of the clock generator, and amplifier.

A disadvantage of the known synchronizer circuit is its lack of reliability.

The aim of the invention is to eliminate this drawback.

This goal is achieved by using a synchronizer of friction and cam clutches, which contains a control unit, (+1) whose inputs are connected respectively to the outputs of n digital bits and to the output of the sign bit of a reversible counter, (n - {- 2) and () inputs - with the first and second outputs of the clock, and the outputs - with the third input of the switching unit and the amplifier input.

The drawing shows a block diagram of a synchronizer incorporating friction n cam clutches.

The proposed device contains a reversible counter 1, a control unit 2, a clock pulse generator 3, a differentiating amplifier 4, an amplifier 5, a switching unit 6, frequency sensors 7 and 8, pulse shapers 9 and 10, a relay 11 and contacts 12

relay.

The principle of operation of the synchronizer is as follows.

The main element of the circuit is a reversible counter I. The state of the counter is monitored by control unit 2. The latter is controlled by potentials from the forward and inverse outputs of the clock generator (GTI) 3.

When the GTI is transferred to the state O (the beginning of the counting time) by a pulse from the differentiating amplifier 4, the counter is reset. Potential from the right (according to the diagram) output of the control unit

(CU) 2, the settler 5 is turned off, and the potential from the left output switches on the switching unit 6 for passing pulses to the counting inputs of counter 1.

When the difference in speed (frequency) is large,

then the counter is filled with a difference much earlier than the end of the counting clock. At the moment of filling the counter, the output potential. The CU switching unit 6 is turned off, and the pulses to the counting inputs do not pass, and the amplifier 5 is still de-energized.

In this state, the circuit is held for the remainder of the counting clock (GTI in the state "O") and for the interval following this clock (GTI) in the state "1).

At the time of the next GTI change to the state "About the counter, it is again set to its initial state, and the cycle is repeated.

When the difference in revolutions decreases so much that the source is empty at the end of the counting clock (synchronous or almost synchronous rotation), the inhibiting signal for amplifier 5 does not form at the output of the control unit (there is a permit) and the GTI moves to the state "1 (end of the counting clock) the amplifier 5 is turned on, and the switching unit b is locked. The contacts 12, the relay 11, turned on at the output of the amplifier 5, close, create a circuit for the passage of a command to turn on the couplings.

Contacts remain closed while the GTI is in the state "1. With his transfer to the state of "O difference counting cycle (A / l; 0)

and the subsequent closure of the contacts is repeated.

Subject invention

A synchronizer of friction and cam clutches, containing two pulse drivers, the outputs of which are connected respectively to the first and second inputs of the switching unit, the outputs of which are connected respectively to the first and second inputs of the reversing counter, the first output of the clock generator connected to the third input, and an amplifier different

in order to increase the reliability of operation, it contains a control unit, (n + 1) whose inputs are connected respectively to the outputs n of the digital bits and to the output of the sign bit of the reversible counter,

(“+2) and (r + 3) inputs — with the first and second outputs of the clock generator, and outputs — with the third input of the switching unit and the amplifier input.