SU402052A1 - DEVICE FOR CODING INFORMATION - Google Patents

Description

one

The invention relates to digital automatic devices and can be used, for example, in remote control devices for dispersed objects in irrigation and drainage systems.

Devices for encoding information containing a clock pulse generator, an 8-bit distributor, a scaling circuit, a binary number code register, modulo-two adders, OR and C logic circuits, polling pulse generators, memory cells and a reset unit are known .

However, the design of such devices is complicated with an increase in the number of bits of the source binary code.

In order to eliminate this drawback in the proposed device, the outputs of the binary number code register through the “OR” circuits are connected to the inputs of the AND logic and the input of the modulo two. The output of the eighth distributor cell is connected via a key to the input of a scaling circuit, the outputs of which are connected to the register input and through the OR circuit to the control input of the key. And to the input of the key through the scheme "OR connected to the outputs of all the cells of the distributor.

The drawing shows the block diagram of the proposed device.

The device contains a clock pulse generator 1, a distributor 2 for 8 bits, a scaling circuit 3, a binary code register number 4, adders 5-8 modulo two, logic circuits "OR 9-18, keys 19-26, polling pulse generators 27- 32, ferrotransistor cells (FTA) 33-36, logic “And 37-39 and the reset unit 40.

The device works as follows. Assume that the initial eight-bit binary code of the transmitted information is recorded in register 4, and all keys 19-26 are closed.

When a control command is received on the keys 19, 20, the latter are opened, the clock pulses from generator 1 through key 19 are input to the serial readings of register 4. In each clock of the generator, one bit of the source binary code is sequentially read through key 20 zi

When a control command is received at the inputs of the keys 21, 22 and 23, the latter are opened. The clock pulse of the generator 1 is fed to the distributor 2, and the first pre-prepared cell is triggered. At the same time, the clock pulse is fed to the input of parallel reading of the first tetrad of the binary code of the register information 4.

At the same time, the parallel reading of four bits of binary code from register 4 is recorded and entered into logic circuits AND 37-39 and adder 7. A unit removed from the nerve cell of the distributor is written through logic circuits OR 13-15 in FTIA 33 -35, performing the functions of a storage device. It should be noted that the remaining seven outputs of the distributor 2 are connected to the inputs of the OR 13-15 circuits in accordance with the possible combinations of the three bits.

The inputs of the circuit “OR 16 are connected to the outputs of all the cells of the distributor 2.

The blocking generators 27, 28, triggered by a clock pulse, poll FLT 33-35, reading the recorded units on the And 37-39 circuits. The circuits "And 37-39, if the information" 1 from register 4 was recorded on them, gives an intermediate conversion unit to the corresponding adders 5-1. From the output of the adder 7, after the blocking generator 31 has been triggered, the first bit of the 16-bit Reed-Muller code is read. The described operations occur in the time interval between two clock pulses. The process of generating the code is repeated in a similar manner for eight cycles. After forming the eighth bit of the Reed-Muller code, the reset unit 40 generates a pulse that resets the AND 37-39 circuits. In this case, a command is sent to the input of a parallel reading of the second tetrad of the source binary code of register 4, which reads from register 4 and goes into the And 37-39 circuits of the next four bits of the source binary code.

Formation of the remaining eight bits

The Reed-Muller code is similar.

Successively formed sixteen bits of the Reed-Muller code arrive

through key 22 into the communication channel.

When a control command is received at the inputs of the keys 21, 24-26, they open. In this case, the conversion circuit 3 is connected in series to the distributor 2. Recording units from the cells of the distributor 2 can be carried out through the OR 13-16 logic circuits in FLF 33-36. In the first cycle, a command is issued and the reading is performed.

the first tetrade code information from register 4 is similar to that described.

Eighth, as well as the operation of the eighth cell of the distributor 2, the first counting pulse arrives at the input of the rec5 of even circuit 3. From the output of circuit 3 to key 25 through the scheme “OR 17 nostunet impulse closing key 25. For the next eight cycles from the outputs of the distributor,

10 units are delivered through the schemes “OR 13-1B in FTYa 32-34, while there are no entries in FTYa 35 which is equivalent to storing in it“ O. And the 16th clock after the second triggering of the eighth distributor cell 2 to the input of the circuit.

5 3 a second counting pulse arrives, from the output of the circuit 3 a pulse is fed to the input of the parallel reading of the second tetrad of the register 4 information code and through the OR 17 circuit to the key 24, which is opened.

0 Thus, the formation of 32 bits of the orthogonal Reed-Muller code occurs in the same way as described for 16 bits, except that the reset of the “And 37-39” circuits and the reading of the second tetrad of bits

5 binary code of information from register 4 is carried out in the 16th cycle of operation of generator 11. In addition, the sequentially generated 32 bits of the Reed-Muller code are read into the communication channel

0 after the blocking generator 32 is triggered from the adder 8 via the key 26.

Subject invention

A device for encoding information

5 containing a clock generator, distributor, scaling circuit, binary number code register, modulo-two adders, OR, AND, keys, polling pulse generators storing

0 cells and a reset unit, characterized in that, in order to simplify the device, therein the outputs of the binary number code register through the OR circuit are connected to the inputs of the AND logic and the modulo-two input.

5 the output of the last distributor cell is connected via a key to the input of the scaling circuit; the outputs of the scaling circuit are connected to the register input and through the circuit "OR to the control input of the key; and to the entrance

0 key through the circuit "OR connected to the outputs of all the cells of the distributor.

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