SU386424A1 - DEVICE TO REDUCE THE EXCESS RATE OF DISCRETE SIGNALS - Google Patents

Description

one

This invention relates to the field of telemetry.

Devices are known to reduce redundancy in the transmission of discrete signals. They are intended for ALS transmission of extreme values of functions and consist of an analog-to-digital converter, a delay element, a coincidence circuit, a main memory, an increment sign analyzer, additional memory, a control circuit. Such devices have low accuracy of data transmission.

The purpose of the invention is to improve the accuracy by transmitting all essential samples. This is achieved by the fact that a controlled pulse generator is included in the device, the sample numbering unit is connected to the input, and a memory device connected to an adder connected to one of the outputs of the comparison circuit is connected to the output.

The drawing shows a block diagram of the proposed device.

The device contains block / numbering counts; a controlled generator of 2 pulse pulses, including a counter of 3 pulses, a diode, 4, a trigger 5 and a generator of 6 counting pulses; adder 7, memory devices (memories) 8, 9 and 10, circuit // comparison, block / 2, approximation accuracy, circuits

13 and 14 of the prohibition, control circuit 15 and input blocks 16 and 17.

In the initial state, all the triggers of the numbering unit 1 are in the state corresponding to one, and the triggers of the counter of 3 pulses are in the position corresponding to zero. The pulses at the input of the charger 8 and the pulse counter are absent, since the valve (diode) 4 is closed by the trigger 5. The charger is cleared,

adder 7 is set to zero and the inhibit circuits are closed.

During operation of the device, the input block 16 receives a sequence of clock pulses of samples, the input block / 7-

sample values in digital form. Block

counting numbers counts clock

impulses, determine the number of each reference.

Simultaneously with the arrival of a certain

clock pulse code corresponding to

The reference number is written to the pulse counter in the reverse code. After some time delay, trigger 5 opens valve 4. Counting pulses from generator 6 begin to flow to the counter input and readout memory bus 8. When the counter overflows, a counting stop signal is generated. With this signal, trigger 5 is reset. The valve is closed. The number of pulses in the produced pulse train

corresponds to the number of the 1st count.

At the beginning of the device operation cycle, the code of the first count r / o is entered into memory 9, and the second count code у is entered into memory 10. The control circuit 15 does not pass the codes of numbers r / o and r / i into the adder 7. Code of the third count r / i enters the adder, where, taking into account the code of the second count called from the memory 10, the current increment Aus Ul – U is determined. After the delay time required to perform this operation in the adder, the g / g code is written in the memory 10 instead of the g / i code. / g is sent to memory 8.

The prediction of the increment value is made by adding the current increments of Ag / g in the adder. For this, the code Ar / 2 is entered into the adder twice by pulses from the generator 6. Then the true increment is determined on the segment in two time intervals Dg / 2: t / z - W0 with a call to the adder of numbers from the memory 5 and / 0. The sum of A 2Ag / s - Ar / 2 is formed in the adder. The resulting algebraic sum A is fed to a comparison circuit 11, to another input of which digitally receives the number b, which specifies the measurement accuracy.

If the number A in absolute value is less than the number b, then there is no signal at the output of the comparison circuit. In this case, the device retains its state until the next measurement, g / 3. The cycle of operation is repeated.

The current increment A g /, g / z-g / 2 is then calculated - the predicted increment on the site in three time intervals Zag / s The true value of the increment Ar / z g /, g / j on this interval and the algebraic sum D ZDg / s - Ag / s. A comparison is made modulo the values of A and B.

Thus, in the general case, for i-ro + 1 readout, the condition is checked

/ (i / i-fi -i //) f - (g / -t / e),

If this condition is not met, i.e., the value of A is greater in absolute value of the number 6, then a signal appears at the output of the comparison circuit. With this signal, the numbering unit of the samples is set to the initial state (all triggers are switched to one), the ban is removed from circuits 13 and 14. The measurement of g / g passes through the prohibition circuit 14 on the output of the device, and the measurement of g / i + i through Schemes. 13 of the prohibition is recorded in memory 9 as the initial (first) readout r / o for the next measurement cycle.

Subject invention

Claims (2)

1. A device for reducing the redundancy of discrete signals, containing input blocks and a numbering unit of samples, one input of which is connected to the circuit outputs comparison and prohibition circuits, the inputs of the comparison circuit are connected respectively to the outputs of the precision setting unit and the adder, and the inputs of the prohibition circuits are connected through memory devices to the inputs of the adder, one of the inputs of which are connected with the output of the control circuit, characterized in that, in order to increase the accuracy of monitoring the redundancy of discrete signals and the availability of work, a pulse burst generator is entered into it, the inputs of which are connected respectively to the outputs of the numbering unit of the samples and the input unit, and the output through the memory The device is connected to the input of the adder. 2. The device according to claim 1, characterized in that the pulse generator contains a pulse counter, a diode, a trigger, and a counting pulse generator, the output of the counting pulse generator is connected via a diode to the trigger output and to the pulse counter input, the output of which is connected to the trigger input. Vylod