SU1764160A1 - One side refusal logic element - Google Patents

Description

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(21) 4666634/21 (22) 02.28.89 (46) 09.23.92. Bul No. 35

(71) Mine Yubileyna Rostov Production Association for the extraction of coal

(72) A.V.Stepanov and V.A.Stepanov (56) USSR Author's Certificate No. 1236605, cl. H 03 K 19/14, 1986.

Copyright certificate NRB 31631, cl. H 03 K 19/00, 1982. (54) LOGICAL ELEMENT WITH UNIQUE ERRORS

(57) The invention relates to a pulse technique and can be used in the manufacture of automation devices for critical technological processes. The aim of the invention is to increase the reliability of the element by simplifying its device and reducing the number of power sources. In the description of the invention, there are 8 figures representing a schematic diagram of the proposed logical element with one-sided failures, and a description of the operation of the device. 8 il.

The invention relates to the field of pulsed technology and can be used to build automation devices for critical technological processes.

The purpose of the invention is to increase reliability by simplifying the device and reducing the number of power sources.

Figure 1-8 presents the schematic diagram of the device.

The logic element in FIG. 1 contains a power source, a positive bus 1, a resistor 2, the first 3 and second 4 diodes, a capacitor 5, the first 6 and the second 7 key elements with optical inputs 8 and 9, respectively, the common bus 10 of the power source, an LED 11, which is optically coupled to the third key element 12, third diode 13, transformer 14, incandescent bulb 15, optical shutter 16. Positive power supply bus 1 through a resistor 2 is connected to the anode of the first diode 3, the cathode of which is connected to the anode of the second 4 diode through capacitor 5, ne The first pin of the first 6 key element is connected to the anode of the first diode 3, and the first pin of the second 7 key element is connected to the cathode of the first 3 diode, the second pin of the first 6 key element is connected to the anode of the second 4 diode, optical inputs 8 and 9 of the first and second key elements are the inputs of the device, the second output of the second 7 key element is combined with the cathode of the second 4 diode and connected to the common bus 10 of the power supply to which the cathode of the LED 11 is connected, the anode of which is connected to the anode of the first 3 diode, the first output of the three In addition, the key element 12 is combined with the anode of the third 13 diode and the first primary output, the transformer 14 windings, the third 13 diode cathode and the second primary output winding of the transformer 14 are connected to the positive bus 1 of the power source, the secondary winding of the transformer 14 is connected to the glow lamp 15. which optically connected to the optical input of the optical shutter 16, the optical

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the output 17 of which is the optical output of the device, and the electrical inputs 18 and 19 of the optical shutter 16 are the clock inputs of the device.

The device works as follows.

In the case of the implementation of the logical function And the inputs 8 and 9 are logic signals. A logical unit corresponds to a sequence of light pulses, the frequency of which is equal to the frequency of the pulses at inputs 18 and 19, the absence of light pulses corresponds to a logical zero.

Assuming logical units are present at inputs 8 and 9, then key elements 6 and 7 begin to switch at the clock frequency. When keys 6 and 7 are open, capacitor 5 is charged along the circuit; positive bus 1, resistor 2, diode 3. diode 4, common bus 10 When keys 6 and 7 are closed, capacitor 5 is discharged through LED 11. At the same time, the duration of light pulses at the optical output of LED 11 will be less than the duration of clock pulses due to the rapid discharge process of the capacitor 5. To normalize the duration of the light pulses at the output of the logic element, the signal from the optical output of the LED 11 goes to the third 12 key element, the load of which is a transformer 14. The pulse signal is amplified and n It is given on the incandescent bulb, which has large inertia, so it emits a constant luminous flux is converted into light pulses, the repetition period and the duration of which is equal duration and the repetition period of clock pulses from the inputs 18 and 19.

Thus, with two single logical signals at the inputs, at the output of a logic element a signal of a logical unit takes place.

Assume that input level 8 (9) is at a logic zero level, and input 9 (8) is a logical unit, then one of the key elements of ± 6 (7) is permanently open, so capacitor 5 will be continuously charged and cannot be discharged through the LED 11. The situation is similar with two logical zeros at inputs 8 and 9. In these cases, there are no light pulses at the output of the logic element, which corresponds to a logical zero.

Thus, the logical element performs the logical function of the conjunction. A logical element can implement a logical function OR, if the inputs 8

and 9 of the first 6 and second 7 key elements simultaneously signals from at least one source of input signals. Figure 2 shows the possible implementation of an AND element having one less diode compared to that described above, and FIG. 3 shows an embodiment of an OR element having one diode and one key element less.

0 Figure 4 and Figure 5 show the implementation of a key element with an optical input on field-effect transistors with an insulated gate and on a field-effect transistor, the photodiode is included in the gate circuit.

5 FIGS. 6, 7, and 8 show diagrams of performing more complex logical devices based on a logic element with one-sided failures, shown in FIG. So on Fig.6 elements 20 (23, 25) and 21

0 (22, 24) And and OR elements with unilateral failures, 26-33 device inputs, 36-39, the corresponding outputs of elements 20-25, respectively. This device implements logical functions

5F (with v d) v ab and F (a v B) cG d.

Figure 7 shows the use of logical elements OR with one-way failures for the purpose of reserving blocks 40 (46), 41 (47), outputs of which are 42 (48), 43 (49)

0 are connected to the inputs of the elements OR 44 with the output 45 and 50 with the output 51, and in FIG. 8, blocks 52, 53, 54 are reserved, the outputs of which are connected to the element 55 OR using the buses 56, 57, and using the buses 58.

5 59 to the element OR 60.

Claims (1)

The invention includes a logic element with one-side failures, containing a power source, a resistor, a LED, a first and a second diode, a capacitor, and a first and second key element with an optical input, characterized in that, in order to increase reliability by simplifying the device and reducing the number of sources a power supply, a third key element with an optical input, a third diode, a transformer, an incandescent lamp and an optical gate, the resistor is connected to the positive terminal of the power supply source by the first output, the second output is connected to the anode of the first diode, the cathode of the LED and the first output of the first key element, the cathode of the first diode is connected to the first output of the second key element (, 5 that directly and through a capacitor to the second output of the first key element combined with the anode of the LED, the second output of the key element and the common power supply bus, optical the inputs of the key elements are the optical inputs of the logic element, and the optical output of the diode is optically connected to the optical input of the third key epemming, the first output of which is combined with the first output of the transformer primary winding and the anode of the third diode, the cathode of which is combined with the second output of the transformer primary winding Fig 2 the torus and connected to the positive power bus, the transformer secondary winding is connected to an incandescent bulb, the optical output of which is connected to the optical input of the optical shutter, the optical output of which is the output of the device, and the electrical inputs of the optical shutter are clock inputs of the device, Phie. / Fig.Z FIG. 7 a1 / 53 al ffS / # az 56 47 -55 a 58 60 " about Fig.8