SU1762254A1 - Device for measuring harmonic signal frequency - Google Patents

Abstract

The invention can be used to measure the frequency of a harmonic signal in a time shorter than the period of the measured signal. The aim of the invention is to improve the accuracy of measuring the frequency of a harmonic signal. The device contains an analog-digital converter 1. the first - third registers 2, 3, 4, the adder 5, block 7 determining the module number, block 8 comparison, the first block 9 prohibition, the first block 11 dividing, functional block 13, pulse generator 15, the first and second blocks 16, 17 delay, the introduction of block 6 of the multiplier by two. the second block 10 prohibition and block 14 of the memory allows to increase the measurement accuracy. 1 silt

Description

The invention relates to a measurement technique and is intended to measure the frequency of a harmonic signal in a time shorter than the period of the measured signal.

The aim of the invention is to improve the accuracy of measuring the frequency of a harmonic signal.

The drawing shows a functional diagram of a device for measuring the frequency of a harmonic signal.

The device contains an analog-to-digital converter 1 (ADC), the first - the third registers 2, 3, 4 shift, adder 5, multiplier 6 by two, block 7 determining the module number, block 8 comparison, the first and second blocks 9,10 ban, the first and a second block 11.12, dividing function block 13, memory block 14, pulse generator 15, first and second delay blocks 16, 17.

The output of the ADC 1 is connected to the input of the first shift register 2, the output of which is connected to the input of the second shift register 3,

the output of which is connected to the first input of the adder 5, the second input of which is connected to the output of the first shift register 2, and the output is connected via serially connected first delay block 16 and block 9 to the first input of the first division block 11, the second input of which is connected to the output of the second register 3 shift through serially connected multiplier 6 by two. the second delay block 17 and the prohibition block 10, while the output of the second shift register 3 is connected to the input of the module 7 for determining the module number, the output of which is connected to the input of the comparison unit 8, the output of which is connected to the control inputs of the prohibition blocks 9, 10, and the output of 11 divisions are connected to the input of the functional unit 13, the output of which is connected by the sperm input of the second division unit 12, the second input of which is connected to the output of the memory block 14, the output of the pulse generator connected to the control input of the ADC 1 and the additional inputs ditch 2,3,4 shift

J

V |

O Yu N0 J J

The device works as follows. The monitored voltage U is fed to the analog input of the ADC 1, which transforms the instantaneous values of the monitored voltage into a digital code with a period. This code enters and sequentially fills the registers 2, 3, 4 shift. Thus, in the steady state in the shift register 4, the code Ui is located, in shift register 3 there is the code U and in shift register 2 there is the code Uz, where Ui, U, Uz are the instantaneous values of the monitored voltage at times ti, t2, tc respectively. The contents of the first shift register 2 From the third shift register 4 and Ui are summed in the adder 5 and the result through the first delay unit 16 and the prohibition block 9 is fed to the first input of the first division block 11. The content of the second shift register 3 U, after multiplying by two in the multiplier 6, is fed through the second delay block 17 and the block 10 against the second input of the first division block 11. Simultaneously, the signal U2 goes to block 7 for determining the modulus of a number and after it to block 8 for comparison, where I Da I cf is annihilated by a threshold (for example, h is 0.1 lUal, U2 is the normalized value of the signal).

If lU2i h. then the comparison unit 8 produces a low potential and closes the prohibition blocks 9, 10. In this case, the codes of the previous samples are saved at the outputs of blocks 9. 10 of the prohibition, and at the output of the device - the code of the previous result. When U2 S h blocks 9. 10 prohibitions pass codes Ui + Us and 2U2 to the inputs of block 11 division. The result of the division enters the functional block 13. where the function is calculated

Ui + U3 D. to, "arccos -om- Second block 12 division

performs the operation of dividing the signal received from the output of the functional unit 13 by the value of the signal 2L, T0. recorded in memory block 14. At the output of the second division unit 12, the value is obtained

, 1Ui + Ua

frequencies equal to t - tm-r-arccos-gp

) 2

Thus, by introducing an additional circuit connected in parallel with the U2 signal passing circuit and containing a unit for determining the module number, a comparison unit and two prohibition units, it is possible to forcibly interrupt the flow of signals leading to large measurement errors to the inputs of the unit. dividing, which ultimately leads to an increase in the accuracy of measuring the frequency of the harmonic signal,

F o rm a and z b per e n i

A device for measuring the frequency of a harmonic signal, containing an analog-to-digital converter, the output of which is connected through the first, second and third registers connected in series to the first input of the adder, the second input of which is connected to the output of the first register, as well as the unit for determining the number module, the first and second blocks delays, the comparison unit, the output of which is connected to the control input of the first prohibition unit, the first division unit, the functional unit, the output of the pulse generator connected to the additional the first register and the control input of the analog-to-digital converter, whose information input is the device input, characterized in that, in order to improve the measurement accuracy, a multiplier by two, a second inhibit unit, a second dividing unit and a memory block, an output are entered into it which is connected to the second input of the second dividing unit, the first input of which through the functional

the converter is connected to the output of the first dividing unit, the output of the pulse generator is connected to the additional inputs of the second and third registers, the output of the second register is connected to the inputs

a multiplier for two and a unit for determining the modulus of a number, the output of which is connected to the control input of the second prohibition unit through a comparison unit, the output of the multiplication unit by two through a serially connected second delay unit and the second prohibition unit is connected to the second input of the first division unit, the first input of which through the serially connected first block and the first block of the delay connected

0 with the output of the adder.

Claims (1)

10 claims A device for measuring the frequency of a harmonic signal containing an analog-digital converter, the output of which is connected through a series of first, second and third registers to the first input of the adder, the second input of which is connected to the output of the first register, as well as a unit for determining the number module, the first and second delay blocks , a comparison block, the output of which is connected to the control input of the first inhibit block, the first division block, a functional block, πρί, whereby the output of the pulse generator is connected to an additional the first register and the control input of the analog-to-digital converter, the information input of which is the input of the device, characterized in that, in order to increase the accuracy of measurements, two multipliers are introduced into it, the second block is inhibited, the second division block and the memory block, output which is connected to the second input of the second division unit, the first input of which through the functional 35 converter is connected to the output of the first division unit, the output of the pulse generator is connected to additional inputs of the second and third reg strov, the output of the second register is connected to the inputs 40 of the two multiplier and the number module determination block, the output of which through the comparison unit is connected to the control input of the second inhibit block, the output of the multiplier by two through the second delay block and the second inhibit block connected in series with the second input the first division block, the first input of which is connected in series through the first block of the ban and the first delay block is connected to the output of the adder. Compiled by E. Soloviev Editor Tehred M. Morgenthal Corrector S.Jusco Order 3257 Circulation Subscription VNIIIPI of the State Committee for Inventions and Discoveries under the State Committee for Science and Technology of the USSR 113035. Moscow, Zh-35, Raushskaya nab., 4/5 Production and Publishing Plant Patent, Uzhhorod, 101 Gagarin St.