SU1404973A1 - Mean-value digital phase meter - Google Patents

Abstract

This invention relates to a radio measuring technique. The digital phase meter contains adjustable amplifiers 1 and Z, comparators 3 and 4, forming unit 5, D-flip-flop 6, oscillator 7 clock pulses, element 2I-HE 8, counter 9 pulses and buffer register 10. Introduction of adders 11 and 13, multiplexer 12 and the buffer registers 14 and 15 allow for improved measurement accuracy by averaging the measurement results over the n previous measurement cycles. In addition, the device allows to obtain constant information about the measurement result and changes in the control signal values at the control input of the multiplexer 12 and quickly change the averaging of the measurement results both from the magnitude of the noise in the voltage being tested and when the frequency of the voltage being tested changes. 1 il. c (o

Description

four; about

four

WITH

- with

The invention relates to a radio metering technique and can be used to measure the average value of the phase shift between two-periodic voltages.

The purpose of the invention is to increase the measurement accuracy.

The drawing shows a phase meter diagram.

The digital phase meter of the average phase shift contains the first 1 and second 2 adjustable amplifiers, the first 3 and second 4 comparators, the forming unit 5, D-flip-flop 6, the generator 7 also {5 current pulses, the logic element 2I-HE 8, the counter 9 pulses the first buffer register 10, the first adder 11, multiplexer 12, the second adder 13, the second 14 and the third 15 buffer registers 20, the reference voltage input 16, the voltage input 17, the multiplexer control input 18, the digital phase meter output 19. ,

Moreover, the input of the first regulated

amplifier 1 is the input voltage of the reference voltage, and the input of the second regulated amplifier 2 is the input .17 of the digital phase meter voltage under investigation, the input of the first comparator of the SZW is connected to the output of the first adjustable amplifier 1 and its output to the input of the forming unit 5, the output of which is connected to the installation inputs of the trigger 6, the pulse counter 9 and 35 with the counting inputs of the first 10, second 14 and third 15 buffer registers, the first input of the second comparator 4 is connected to the output of the second adjustable amplifier 2, the second inputs up to maratory connected to a common bus, the output of the comparator 4 is connected to the counting input of the D-flip-flop 6, the information input of which is connected to the common bus, and its output is connected to the first input of the logic element 2I-HE 8, the second input of which is connected to the generator 7 clock pulses, and the output with the counting input of the counter 9 pulses, the outputs of the bits of the last Q are connected to the information inputs of the first buffer register 10, the outputs of which are connected to the first inputs of the first adder 11, the second inputs of which are connected to the outputs of the second bu The ferronic register 14, the information inputs of the multiplexer 12 are connected to the outputs of the adder 11, and the outputs of the multiplexer are connected to the second inputs of the second adder 13, the outputs of which are connected to the information inputs of the second 14 and third 15 buffer registers, the outputs of the third buffer register 15 are digital outputs of the phase meter, moreover, the control inputs of the multiplexer 12 are control inputs 18, setting the averaging factor of the measurement results.

Phase meter works as follows.

In the code of the digital phase meter, which measures the instantaneous value of the phase shift, a digital filter is applied, consisting of two binary Adders, one multiplexer and two buffer registers. The digital filter works according to the following algorithm:

(n-H) (n + 1) -Ncp ,,

where Nj-p is the average value of the measurement results obtained for the n previous measurement cycles;

N (.p (n + 1) is the average value of the results of the measurements obtained as a result of the last measurement;

N (n + 1) is the result of measurements obtained in the last measurement cycle; F - averaging coefficient

(smoothing).

The averaging coefficient is related to the period of the studied oscillation T and the equivalent constant chain with the following relation:

- En-fr 1

It follows from the relation that in order to obtain a constant value of an equivalent constant circuit, when the frequency of the voltage under study is changed, it is necessary to change the coefficient of averaging.

Adjustable amplifiers 1 and 2 establish the voltage amplitude ensuring the normal operation of comparators 3 and 4. When the voltage coming from input 16 exceeds the zero level, a high logic level is set at the output of the comparators (hereinafter 1). On the front of the change in the output state of the comparator by the forming unit 5

3.140

short pulses are formed. The pulses are fed to the setup inputs of the D-flip-flop 6, the counter 9 and the counting inputs of the buffer registers 10, 1A and 15. With the arrival of these pulses, one measurement cycle ends and a new one begins. The generated pulse arriving at the counting input of the buffer registers 10, 14 and 15, writes in them the binary numbers received by them at the information inputs and, entering the installation inputs, sets the D-thrunger 6 1 at the output, and at the output of all bits of the counter 9 - low logic level (hereinafter O). Thus, 1, arriving from the D-flip-flop 6 to the first input of the logic element 2И-НЕ 8, permits the impulses from the generator 7 clock pulses to arrive at the counting input of the counter 9 pulses.

After the signal under test at input 17 exceeds the zero level, the output of comparator 4 is set to 1 and, arriving at the counting input of D-flip-flop 6, records at its direct output O. This input signal to the first input of logic element 2I- NOT 8, will set 1 at its output and prohibit the passage of such pulses to the counting input of the counter 9 pulses. Consequently, at the outputs of the pulse counter 9, a binary number is recorded, determined by the time between the zero-level transitions of the voltages supplied to the inputs 16 and 17 of the digital phase meter. The result obtained at the beginning of each cycle is written into the buffer register 10, from the outputs of which is fed to the first inputs of the adder 11. The second inputs of the same adder receive the inverted result recorded in the buffer register 14. Thus, the adder 11 performs a subtraction from the result of the binary numbers obtained as a result of previous calculations. The binary number obtained at the output of the adder 11 is fed to the multiplexer 12, which performs a shift by one, two or three bits (divide by two, four, eight). The resulting number at the output of the multiplexer is fed to the second

the inputs of the adder 13, on the first inputs of which enters the binary number recorded in the buffer register 15 and the resulting previous

34

cycles. The result obtained at the output of the adder 13 is a binary number that corresponds to the average value of the measured phase shift

for the previous n periods (cycles). With the arrival of the next pulse formed by the forming unit 5, the result is recorded in the buffer registers 14 and 15 and fed to the output 19 of the digital phase meter.

Input 18 is supplied with a binary number defining the shift performed by multiplexer 12 (for which number

divide), the binary number obtained at the output of the adder 11.

Thus, the proposed phase meter allows one to increase the measurement accuracy by averaging the result of TQB measurements over n previous measurement cycles, to obtain constant information on the result of measurements and a change in the control signal values.

at the control input of the multiplexer, quickly (operatively) change the averaging of the measurement results as from

the magnitude of the noise in the test area, and when the frequency changes

test voltage.

Claims (1)

Invention Formula The digital phase meter of the average value, containing the first and second control amplifiers, the outputs of which are connected to the non-inverting inputs of the first and second comparators, their inverting inputs are connected to the common bus, the output of the first comparator connected to the input of the forming unit, the output of which is connected to the installation input of the D-flip-flop, the installation input of the pulse counter and the counting the input of the first buffer register, the output of the second comparator is connected to the counting input of the D-flip-flop, the output of which is connected to the first input of the logic element 2PI-HE, the second input of the logic element 2I-NOT is connected to the clock generator, the output of the logic element 2I-NOT is connected to the counting the pulse counter input, the pulse counter bit outputs are connected to the infrared inputs of the first buffer register, characterized in that, in order to improve the measurement accuracy, two summations are entered into it 5 1404973 -6 pa, the multiplexer, the second and third adders are connected to the out-buffer registers, the first inputs are first to the third iufernogo register adder connected to the outputs, the outputs of the second adder to the first buffer register, the second ones are connected to the information inputs of the second and third buffer registers, the buffer register, the outputs of the first of their counting inputs are connected to the exhaust accumulator connected to the information unit of the forming unit, and the inputs The multiplexer inputs, which control multiplexer outputs are connected to the first inputs of the digital control input of the digital phase-accumulator, the second inputs of the second meter.