RU2255343C2 - Group delay time measuring unit - Google Patents

Abstract

FIELD: measurement technology.

SUBSTANCE: measuring unit is used for measuring time shifts between output and input signals induced in real four-terminal networks, for example, in amplifiers of audio signals. Measuring unit can be used for measuring as random signals and determined monoharmonic signals. Measuring unit has two extremum selection units which have outputs connected with inputs of time shift measuring unit. Inputs of extremum selection unit have to be inputs of measuring unit. Measurement of time shifts between extreme of output and input signals allows to eliminate errors caused by shifts in signal zero line in four-terminal network and influence of non-linear distortions on shape of output signal.

EFFECT: reduced errors; reduced influence of non-linear distortions.

2 cl, 3 dwg

Description

The invention relates to the field of radio measurements and can be used to measure the time shift occurring in real four-port networks, for example, in audio signal amplifiers, between output and input signals that are both random and deterministic monoharmonic.

As a prototype, as the closest in technical essence, a classic meter (phase meter) is selected, used to estimate relative time shifts in amplifying devices and containing two pulse shapers, a time interval allocation unit and a time shift measuring unit, the output of which is the output of the meter, input the delayed signal is the input of the first driver, the input of the leading signal is the input of the second driver, the outputs of the first and second drivers are connected with responsibly to the first and second inputs of the block allocation time slot, which outputs are connected to inputs of the measurement unit time shifts [Electrical measurements / Ed. A.V. Fremke and E.M. Dushina. - 5th ed., Revised. and additional - L .: Energy, 1980, pp. 243-244, fig. 6.19 a, b].

The prototype implements a well-known method for measuring phase shifts and group delay times, based on the allocation of the moments of crossing the zero line signals and measuring the time shift between the indicated moments - reference time stamps. An essential drawback of both the method itself and the devices that implement it is the error due to the not quite correct determination of the position of the time marks as the same points of the input and output signals, between which the time delay is then measured. So, when the position of the output signal's zero line changes, the time marks generated by the above path will also shift, which will lead to an error in the measurements of the time shift, and hence the group delay time. Moreover, the zero line offset is possible not only in DC amplifiers or in video amplifiers, but also in AC amplifiers, for example, audio signal amplifiers, since a nonlinear transformation with subsequent centering leads to a similar effect (that is, what happens in real amplifiers) . During nonlinear transformation, a constant component appears in the spectrum of the output signal, after which the resulting process on the load shifts along the ordinate so that the areas under the bipolar half-waves are equal - this leads to a shift in time of the formation of the reference time stamps. As a result, with an increase in the nonlinear distortion, the error in measuring the group delay time also increases. Considering that distortions, as a rule, increase with the amplitude of the input signal, the estimate of the sought delay time will also depend on the amplitude of the input signal, while the true value of the group delay time does not change.

The technical result achieved by using the present invention consists mainly in improving the accuracy of estimating group delay time with zero line offset and non-linear distortions.

The technical result is achieved by the fact that in the group delay time meter, which includes a time shift measuring unit, the output of which is the output of the meter, according to the invention two extremum extraction units are introduced, the input of the first one is the input of the delayed signal, the input of the second extremum extraction unit is the input leading signal, the outputs of the first and second extremum extraction units are connected respectively to the first and second inputs of the time shift measurement unit.

To achieve a technical result, the extremum extraction unit contains an analog-to-digital converter, three registers, two binary code comparators, an And element, and three delay elements, the information input of an analog-to-digital converter serves as the input of an extremum extraction unit, the output of which is the output of the And element, the output of the digital converter is connected to the information input of the first register, the output of which is connected to the information input of the second register, the output of which is connected to the information input of the of the first register, the first input of the first comparator is connected, the second input of which is connected to the output of the second register, the first input of the second comparator is connected to the output of the third register, and the second input of the second comparator is combined with the second input of the first comparator, the outputs of the first and second comparators are connected respectively, to the first and second inputs of the And element, the third input of which is connected to the output of the first delay element, the input of which is connected to the clock input of the block, the analog-to-digital clock inputs the new converter and the third register are combined and also connected to the clock input of the block, the clock input of the first register is connected to the output of the second delay element, the input of which is connected to the output of the third delay element, the input of which is connected to the clock input of the block, the clock input of the second register is connected to the output of the third delay element.

The invention is illustrated graphic material. Figure 1 presents the functional diagram of the group delay meter with a connected tested amplifier. Figure 2 shows the timing diagrams explaining the principle of measurement. Figure 3 presents the functional diagram of the block selection of the extremum.

The functional diagram of figure 1 contains two blocks 1, 2 selection of the extremum, block 3 measuring the time shifts and the tested amplifier 4 with a load R _L. The output of amplifier 4 is connected to the input of the delayed signal y (t) of the meter, which (input) is the input of block 1, the output of which is connected to the first input of block 3 for measuring time shifts, the second input of which is connected to the output of block 2, whose input is an input of the leading signal x (t) of the meter and combined with the input of the tested amplifier 4, the output τ * of the meter is the output of block 3.

Functional diagram (figure 3) of block 1 (2) of extremum extraction contains an analog-to-digital converter (ADC) 5, registers 6, 7, 8, comparators 9, 10, element 11 and delay elements 12, 13, 14. The information input x (t), y (t) of the ADC 5 serves as the input of the block, the output of which is the output of the element And 11, the output of the ADC 5 is connected to the information input of the register 6, the output of which is connected to the information input of the register 7, the output of which is connected to the information input register 8, the input A of comparator 9 is connected to the output of register 6, the input of which is connected to the output of register 7, the input A of comparator 10 is connected to the output of register 8, and the input B of comparator 10 is combined with the input B of comparator 9, the outputs of comparators 9, 10 are connected respectively to the first and second at the inputs of the element And 11, the third input of which is connected to the output of the delay element 14, the input of which is connected to the clock input CLK of the block, the clock inputs of the ADC 5 and register 8 are combined and also connected to the clock input of the CLK block, the clock input of the register 6 is connected to the output of the element 12 delay, the input of which is connected to the output of the delay element 13, the input of which is connected to the clock input CLK of the block, the clock input of the register 7 is connected to the output of the delay element 13. The output of the ADC 5, the information inputs and outputs of the registers 6, 7, 8, as well as the inputs of the comparators 9, 10 are multi-bit and are designed to work with parallel codes.

Timing diagrams (Fig. 2) contain the input x (t) and output y (t) signals of the tested amplifier 4 under the assumption that the group delay time is zero (Fig. 2a), and the amplifier 4 has the properties of a nonlinear four-terminal network; input x (t) and output y (t) signals of the tested amplifier 4 under the assumption that the group delay time is different from zero and equal to τ (Fig.2b), and amplifier 4 has the properties of a nonlinear four-terminal network.

The principle of operation of the meter (Fig. 1) at the functional level is quite simple and consists in the allocation by blocks 1, 2 of the extremum points of the input x (t) and output y (t) signals, and then measuring the time shift τ between them in block 3. Measurement of time shifts between extrema allows you to get rid of errors caused by vibrations (offsets) of the zero line and the influence of nonlinear distortions on the shape of the output signal. From the graphs shown in figa, it can be seen that with nonlinear amplification, even in the complete absence of time delay, the points of intersection of the zero line with the input x (t) and output y (t) signals are located in different places. As for the location of the extrema, they do not shift with slight nonlinear distortions, as well as when the position of the zero line changes. For these reasons, to measure the group delay time or phase shifts, it is advisable to select the extremum points and measure the time distance between them, as shown for the case of modeling the nonlinear amplification of the random process in fig.2b.

One of the options for block selection of the extremum is a device (figure 3), which allocates an extremum in the region of positive values at three adjacent points.

Such a device works as follows.

An analog signal to be sampled and quantized is input to the ADC 5, for example, x (t), the readings of which are successively recorded in registers 6, 7, 8. Through the first three clock cycles from the start of the ADC 5 clock, the first sample x (t ₁ ), in register 7 - the second sample x (t ₂ ) and in register 6 - the third - x (t ₃ ). The obtained samples are compared in comparators 9 and 10. If you enter the comparison operator R, then you can show that the comparators 9, 10 are used to perform operations:

x (t ₁ ) Rx (t ₂ ) and x (t ₂ ) Rx (t ₃ )

or in general terms

x (t _i ) Rx (t _{i + 1} ) and x (t _{i + 1} ) Rx (ti + 2).

If during the comparison process it is established that

x (t _i ) <x (t _{i + 1} ) and x (t _{i + 1} )> x (t _{i + 2} ),

then a decision is made on the presence at the point t _{i + 1 of an} extremum. At the same time, high logical levels are set at the outputs of comparators 9, 10 and, accordingly, an impulse arises at the output of element 11. 11. As a comparator, a 1564 SP1 chip can be used, which is a three-level discriminator that forms the sign “more”, “less” with the corresponding sign of difference input operands [Avanesyan GR, Bespalov A.A. Unipolar integrated circuits. Reference manual - M .: Radio and communications, 2003, pp. 169-170].

For the correct recording of samples, clock pulses are sent to registers 6, 7 with some delay relative to the clock inputs of the ADC 5 and register 8. The presence of delay elements 12, 13 allows sequentially transferring information from register 7 to register 8, then from register 6 to register 7 and only after that put in register 6 a new sample formed in this clock at the output of the ADC 5. The delay time of the elements 12, 13 is selected based on the speed of the registers and the conversion time t _pr ADC. In this case, the condition T> t ₁₂ + t ₁₃ > t _ol (T is the repetition period of clock pulses at the input CLK, t ₁₂ is the delay time in element 12; t ₁₃ is the delay time in element 13). Delay element 14 is necessary for shifting the moment of outputting the output pulse of the presence of an extremum by the time for which the information in registers 6, 7, 8 has time to update, that is, the indicated delay time should be less than T and approximately (10-20)% more than the sum t ₁₂ + t ₁₃ .

The algorithm implemented in the described block for extremum extraction allows one to make a decision on the existence of an extremum and determine the position of the extremum not at the time of its formation, but only after it has formed, after about one clock cycle. However, this does not mean that a systematic error equal to approximately T will be present in the measurements. There is no error, since the pulses of the presence of an extremum are shifted by the same time for both the input and output signals, therefore, there may not be a theoretical relative bias. Of course, in practice, to minimize the relative bias (mismatch), it is necessary to synchronously control the operation of the ADC in blocks 1, 2 and, in addition, in the indicated blocks, the parameters of the elements 14 should be as identical as possible.

The use of the described meter can significantly reduce the errors in estimating the group delay time in real devices exhibiting nonlinear properties, as well as at the output of which a zero line shift is possible. It was found that even with a harmonic coefficient not exceeding 6%, errors caused by incorrect selection of the same reference points by means of widely used clipping can reach tens of microseconds. In the considered device, due to the replacement of the clipping operation by the operation of extremum extraction, such errors are already eliminated at the methodological level.

Claims (2)

1. The group delay time meter, which includes a time shift measuring unit, the output of which is the output of the meter, characterized in that two extremum extraction units are introduced into it, the input of the first of them is the input of the delayed signal, the input of the second extremum extraction unit is the leading input of the signal, the outputs of the first and second extremum extraction units are connected respectively to the first and second inputs of the time shift measurement unit. 2. The meter according to claim 1, characterized in that the extremum extraction unit contains an analog-to-digital converter, three registers, two binary code comparators, an I element and three delay elements, the information input of the analog-to-digital converter serves as the input of the extremum extraction unit, the output of which serves as the output of the And element, the output of the analog-to-digital converter is connected to the information input of the first register, the output of which is connected to the information input of the second register, the output of which is connected to the information input of the the third register, the first input of the first comparator is connected, the second input of which is connected to the output of the second register, the first input of the second comparator is connected to the output of the third register, and the second input of the second comparator is combined with the second input of the first comparator, the outputs of the first and second comparators are connected respectively, to the first and second inputs of the And element, the third input of which is connected to the output of the first delay element, the input of which is connected to the clock input of the block, the analog-to-digital clock inputs the inverter and the third register are combined and also connected to the clock input of the block, the clock input of the first register is connected to the output of the second delay element, the input of which is connected to the output of the third delay element, the input of which is connected to the clock input of the block, the clock input of the second register is connected to the output of the third delay element.

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