SU911363A1 - Automatic digital meter of harmonic coefficient - Google Patents

Description

The invention relates to a measurement technique and can be used to automatically measure small values of the harmonic coefficient of sinusoidal signals when measuring electrical parameters of integrated circuits and amplifying devices.

A digital harmonic coefficient meter is known that contains a driver, a frequency multiplier, a key, an analog-to-digital converter (ADC), two setters of orthopan functions, two multiplying digital devices, two counters, three transfer units, a quad, an adder, a square root extractor, code ratio meter and control block C.

The drawback of the device is the low accuracy of the harmonic coefficient measurement at its low values, due to the limitation of the current ADC bit width.

The closest to the present invention is a harmonic coefficient meter containing a control unit, a driver, a frequency multiplier, a key, an analog-to-digital converter, a quad, an adder, the first

transfer unit, square root extraction unit and code ratio meter, initial phase adjuster, two orthogonal functions, two multiplier blocks, two counters, two transfer blocks, two code-voltage converters, a voltage subtraction block, and a scale 2 sampling block.

ten

The disadvantage of this meter is the large size of the device due to the requirements of obtaining high measurement accuracy, by increasing the ADC's size. In addition, the dynamic range of the meter is limited by small values of the amplitudes and frequencies of the measured signal.

20

The measurement error of the harmonic coefficient depends on the level of suppression in the measured signal of the first harmonic, carried out by subtracting from the measured signal

25 formed orthogonal signal.

The relative measurement error 5, due to the error 30 setting the initial phase of the orthogonal signal, can be found in the mathematical expression: b 2 sin -. 100%, where “p is the angle of the phase paccoiviacoBan of the first harmonic and the formed orthogonal signal. When the quantization frequency fuft is equal to, where fx is the frequency of the first harmonic of the measured signal, n is the number of samples, take the signal from the period of its first harmonic, the measurement error exceeds 6.3% if. To obtain S40, l% must be selected, which corresponds to, 5. angular min. The implementation of this accuracy requires a large amount of operational and permanent digital memory. For example, if the number of discretization levels by the amplitude of the measured and orthogonal signals is 1000 (ten binary bits) and p 200 200, then about 2.5 million bits of memory are required to build devices for orthogonal functions of counters and adders. receiving, during one period, the first harmonic of the initial phase of the orthogonal signal with an accuracy of one sample, the initial phase setter must contain at least n / 4 decoders of the phase error angle codes, i.e. in memory of the named setter, it is necessary, with n 6200, to store about 1500 codes with which the calculated code of the phase error angle must be compared. With the number of the sampling level in amplitude equal to 1000, the accuracy of forming the amplitude of the reference signal is 0.1%, and with the number of discretization levels equal to 100, this accuracy does not exceed 1%. The purpose of the invention is to maximize the functionality of the meter in a wide dynamic range of amplitudes and frequency ranges of the measured signal. The goal is achieved in that a meter containing a control unit, two converters, a code-voltage pulse generator, successively connected voltage subtraction block, a block for selecting a scale, an analog-to-digital converter, a quad / adder, the first transfer unit and an extraction block square root, the first master of the orthogonal function, the first multiplier element, the first counter and the second transfer block, the output of which is connected to the second input of the quadrator and the first input of the master initial phase, the second input of which is connected to the input of the first master of the orthogonal function, and the output of the master generator of the starting phase is connected to the input of the second master of the orthogonal function, the output of which is connected to one of the inputs of the voltage subtractor through the first converter the multiplying element, the second counter, the third transfer unit connected to the third input of the quad, the first input of which is connected to the second inputs of the first and second multiplying elements, are entered into a high frequency generator, a variable divider frequency divider, a precise initial phase setting unit, a constant division divider frequency divider, a pulsed phase detector, a transmission ratio changing unit, a reference element, three pulse distributors and three code set registers, and a block input change of the transmission coefficient is connected to the input terminal of the meter, and its output is connected to the second input of the voltage subtraction unit and to the input of the pulse former, the output of which is connected to From the inputs of the pulse phase detector and with the inputs of three pulse distributors, the output of the first of which is connected to one of the inputs of the frequency divider with a variable division factor through the first register of the code set, and the output of the second pulse distributor is connected to the first input of the second register of the code set, the second input It is connected to the output of the first counter, and the output of the second register of code dialing through the block for precise setting of the initial phase X is connected to the second input of a frequency divider with a variable coefficient The third input of which is connected to the output of the high-frequency generator, and the output of a frequency divider with a variable division factor is connected to the second input of the analog-digital converter and to the input of the initial phase setting unit directly and through a frequency divider with a constant division factor - to the second input of the pulse phase detector , the output of which is connected to the second input of the first register of the code set, and the output of the third pulse distributor is connected to the first input of the third register of the code set, the second the input of which is connected through an element of comparison from the adder, and the output of the third register of code set through the second code-voltage converter is connected to the control unit. input block change ratio. The drawing shows a structural diagram of the harmonic coefficient meter.

The meter contains the first pulse distributor 1, the first register 2 of the code set, the divider 3 frequencies with variable division factor, the divider 4 frequencies with a constant division factor, pulse, phase detector 5, high-frequency generator b, the second, pulse distributor 7, the second register 8 of the set code, block 9 for precise setting of the initial phase, the third distributor 10 pulses, the third register set register 11, the second code-voltage converter 12, change block 13, transfer ratio, pulse shaper 14, block 15 Voltage reading, scale selection block 16, analog-to-digital converter 17, quad 18, adder 19, first transfer unit 20, square root extraction block 21, first unit 22 of orthogonal function, first multiplier unit 23, first counter 24, second block 25 transfer, setpoint generator 26. initial phase, second setpoint generator 27 orthogonal function, second multiplication unit 28, second counter 29, third transfer unit 30, first converter CG coagulation voltage, comparison element 32, control unit 33 (control signaling transmission circuit not shown) andinput terminal 34 gauge ..

The device works as follows.

In the initial mode, the counters 24 and 29, the adder 19 and the divider 4 are in the zero state, the code 100 ... O is written in registers 2.8 and 11, a voltage UK, OB is connected to the second input of the voltage subtraction unit 15, The initial phase setpoint generator 26 is assigned to §-0; the divider 3 triggers write the code from the corresponding trigger register 8. The measured signal Ux goes through block 13 to the driver 14 and to block 15. When voltage Ux passes through zero, block 33 control gives permission to start dividing the frequency of the generator 6 by serially connected dividers 3 and 4. the division factor of divider 4 is equal to a constant number n, which determines the number of samples that is produced during the period of the first harmonic from the measured signal, and the division factor of divider 3 is determined by register reg. 2. In the initial mode, the division factor of divider 3 was increased 50% of the maximum possible ratio. At the end of the period of the first harmonic of the measured signal, when the voltage passes again through zero, one is written next to the high register bit 2, and the high bit trigger of register 2 rewrites the potential from the output of the detector 5 to its output.

the upper level is equal to one if the frequency at the output of the divider is higher than the required one and has a level equal to zero if the frequency at the output of the divider 4 is lower than the required one. At the same time, the triggers of the divider 4 are reset to zero, and in the triggers of the divider 3, the pumping code is again recorded from the register 8 through block 9. Thus, in the next period of the measured signal, the divider division factor 3

0 will be 50% different from the previous one. At the end of the next period, a unit is written into the third register 2 trigger, and the trigger that precedes it overwrites

5 output from detector 5. In this case, the trigger will remain in unit if the frequency at the output of divider 4 is higher than the required one and is reset to zero if the frequency at the output of divider 4

0 below the required. Through K-cycles, where K is the number of triggers in divider 3, the output of divider 3 will remove the signal, the frequency of which is equal to the required

5 n-fy quantization frequency. To obtain a quantization frequency setting accuracy of 0.19, it is necessary to have in the divider 3 not less than 10 triggers, which allow to obtain the division factor from 1 to 2 -1

0 1023. The number of frequency setting cycles is 10, the division factor of divider 3 and does not change further.

five

After entering the meter in synchronism with the frequency of the first harmonic of the measured signal, the control unit 33 generates a command to start the meter in synchronization in amplitude. During the transition

0 3 through zero, the calculation of the amplitude of the first harmonic of the measured signal begins. Converter 17 performs quantization of the measured signal with frequency f ". &Amp; , determined by 5 divider 3. Codes of instantaneous values of voltage Ux of the measured signal from converter 17 are sent to multiplying blocks 23 and 28, to the second inputs of which are synchronous

0 numerical value of orthogonal functions with setpoint

22 and 27. Codes of products from the blocks

23 and 28, taking into account the signs, are added to the counters 24 and 29. For the signal under study, the counters 24 and .29 fix proportional values to the imaginary and real components axt and b ,, of the Fourier coefficients for the first harmonic of the measured signal, namely

0

p-Uy (Ug sinf and n -Uii Ue cos,

where n is the number of samples;

Claims (2)

1. Author's certificate of the USSR 379882, cl. G 01 R 23/20, 1971. 2. Authors certificate USSR 564606, cl. G 01 R 23/20, 1975 (prototype).