RU2550309C1 - Device for signals analysis in real time - Google Patents

Abstract

FIELD: instrumentation.

SUBSTANCE: device additionally contains 2 additional assembly groups, each of them contains connected in series ROM unit, analogue-digital multiplier, analogue integrator with reset, and block of absolute signal value determination, where k is total number of scanning sine signals during spectrum analysis, and including of the additional analogue summation unit and output analogue summation unit, where inputs of the included ROM units are connected with outputs of the address generating counter, analogue inputs of the analogue-digital multipliers are connected to the input busbar, outputs of units of signal absolute value determination are connected to inputs of additional analogue summation unit.

EFFECT: increased accuracy of measurements of harmonic component amplitudes.

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Description

The proposed device relates to the field of measurement technology and can be used to measure the magnitudes of the amplitudes and frequencies of harmonic components in the studied signals. In particular, the proposed device can be used to form spectra for speech recognition, spectra for diagnostics of the noise component of working objects, as well as for the formation of acoustic noise spectra for surface and underwater navigation.

Known devices for the analysis of harmonic components in signals, one of which contains a clock pulse generator, a constant memory unit, counters, a pulse shaper, a phase shift unit, a multiplier, an integrator, an absolute signal magnitude extraction unit, an amplitude detector [1], and the second contains an analog low-pass filter, analog-to-digital converter, two digital filters, two frequency measurement blocks, subtraction blocks, adder, multiplier, averaging block, synchronization block [2]. A common feature of these devices is the relatively low accuracy of measuring the amplitudes of the harmonic components.

The closest technical solution to the proposed device is a device for analyzing signals in real time [3], containing a series-connected clock pulse generator with an adjustable frequency, an address generation counter, a cycle counter, a series-connected read-only memory block, an analog-to-digital multiplier, and an analog integrator with reset, absolute signal allocation unit, input bus, output bus, initial setting bus, where the inputs of the read-only memory block are are connected to the outputs of the address generation counter, the input bus is connected to the analog input of the analog-to-digital multiplier, and the initial conditions setting bus is connected to the setting input of the address forming counter, with the setting input of the cycle counter, with the reset input of the analog integrator with reset, and also containing the second group nodes, consisting of a series-connected block of read-only memory, an analog-to-digital multiplier, an analog integrator with a reset, an absolute signal magnitude allocation unit, analogs the adder, circuit I, the signal bus to complete the calculation cycle, the inputs of the permanent memory block being connected to the outputs of the address generation counter, the analog input of the analog-digital multiplier connected to the input bus, and the reset input of the analog integrator with reset connected to the initial setting bus, inputs the analog adder is connected to the outputs of the blocks for highlighting the absolute value of the signal, the output of the analog adder is connected to the output bus, the inputs of the circuit And are connected to the outputs of the loop counter, the output of the circuit And under It is connected to the signal bus to complete the calculation cycle at a given frequency.

This device is adopted as a prototype.

The disadvantage of the prototype is the relatively low accuracy of determining the magnitudes of the amplitudes of the harmonic components in the studied signals, which is due to the orientation of the device design and, accordingly, the use of only two scanning sinusoidal signals in the device.

The technical result of the invention is aimed at improving the accuracy of determining the magnitudes of the amplitudes of the harmonic components in the studied signals through the use of a larger number of scanning sinusoidal signals when performing spectral analysis. This is achieved by the fact that in the known device for analyzing signals in real time, containing a series-connected clock pulse generator with an adjustable frequency, an address generation counter and a cycle counter, two groups of nodes, each of which contains a series-connected read-only memory block, analog-digital a multiplier, an analog integrator with a reset, and an absolute signal separation unit, as well as an analog adder, circuit I, input bus, output bus, installation bus conditions and the bus for completing the calculation cycle, where the inputs of the permanent memory blocks are connected to the outputs of the address generation counter, the outputs of the absolute signal allocation blocks are connected to the inputs of the analog adder, the inputs of the circuit And are connected to the outputs of the cycle counter, the circuit output And is connected to the bus for completing the calculation cycle , the input bus is connected to the analog inputs of analog-to-digital multipliers, the initial conditions setting bus is connected to the installation inputs of the address generation counter, to the installation inputs of the count a loop of cycles and to the reset inputs of analog integrators with a reset, an additional 2 groups of nodes are introduced, each of which contains a series-connected unit of read-only memory, an analog-digital multiplier, an analog integrator with a reset and a block for extracting the absolute value of the signal, where k is the total number scanning sinusoidal signals when performing spectral analysis, and also introduced an additional analog adder and an output analog adder, where the inputs of the permanent memory blocks entered into the device connected to the outputs of the address generation counter, the analog inputs of the analog-digital multipliers are connected to the input bus, the outputs of the absolute signal separation blocks are connected to the inputs of the additional analog adder, the outputs of the analog adder and the additional analog adder are connected to the inputs of the output analog adder, the reset inputs of analog integrators with by reset are connected to the initial setting conditions bus, and the output of the output analog adder is connected to the output bus. This makes it possible to increase the accuracy of determining the magnitudes of the amplitudes of harmonic components in the studied signals due to the use of a larger number of scanning sinusoidal signals when performing spectral analysis.

The calculation of the amplitudes of the harmonic components at a given value of the cyclic frequency in the prototype device is performed in accordance with the formula:

- два сканирующих синусоидальных сигнала с циклической частотой ω и с начальными фазами, отличающимися на $$\frac{\pi }{2}$$

, A - искомая амплитуда гармонической составляющей в исследуемом сигнале на частоте ω, t - текущее время.in which f (τ) is the signal under investigation, sin (ωτ) and $$\sin (\omega \tau +\frac{\pi }{2})$$

- two scanning sinusoidal signals with a cyclic frequency ω and with initial phases differing by $$\frac{\pi }{2}$$

, A is the desired amplitude of the harmonic component in the signal under study at a frequency ω, t is the current time.

It was shown in [3,4] that the relative error in determining the magnitudes of the amplitudes in accordance with formula (1) can reach δ≈21%, which may be unacceptable for some practical applications.

With the introduction of two, four and six additional scanning signals, the determination of the amplitudes of the sinusoidal components in the proposed device is carried out according to the following formulas:

, $$\Delta {\varphi }_2=\frac{\pi }{6}$$

, $$\Delta {\varphi }_3=\frac{\pi }{8}$$

. В общем случае, при применении в устройстве к сканирующих синусоидальных сигналов, из которых два являются основными и применяются в устройстве-прототипе, а к-2 из которых являются вспомогательными и применяются в предлагаемом устройстве для повышения точности измерения величин амплитуд гармонических составляющих в исследуемых сигналах, величины шага сдвига начальных фаз Δφ вспомогательных сигналов относительно основных равны соответственно $$\Delta \varphi =\frac{\pi }{к}$$

.In these formulas, the first lines contain formula (1), i.e. the formula on the basis of which the prototype device is operated. The subsequent lines in formulas (2) - (4) contain records of auxiliary scanning sinusoidal signals that are shifted in the initial phase relative to the initial scanning sinusoidal signals in formula (1), respectively, with step sizes $$\Delta {\varphi }_{\mathrm{one}}=\frac{\pi }{\mathrm{four}}$$

, $$\Delta {\varphi }_2=\frac{\pi }{6}$$

, $$\Delta {\varphi }_3=\frac{\pi }{8}$$

. In the General case, when applied to the device for scanning sinusoidal signals, of which two are the main ones and are used in the prototype device, and k-2 of which are auxiliary and are used in the proposed device to improve the accuracy of measuring the magnitudes of the amplitudes of the harmonic components in the studied signals, the values of the pitch of the initial phases Δφ of the auxiliary signals relative to the main ones are respectively $$\Delta \varphi =\frac{\pi }{\mathrm{to}}$$

.

The justification of the validity of formulas (2) - (4) and, accordingly, the results of checking the validity of these formulas by modeling are given in [4].

The block diagram of the device shown in figure 1. A device for analyzing signals in real time contains a series-connected clock generator 1 with an adjustable frequency, an address generation counter 2, a cycle counter 3, two read-only memory blocks 4 and 5, connected in series with each of the read-only memory blocks 4 and 5, analog-to-digital multipliers 6, analog integrators with a reset 7, blocks for extracting the absolute value of signal 8, and also contains an analog adder 9, circuit I 10, input bus 11, initial setting bus 12, output bus 13, signal a bus 14 for completing calculations at a given frequency, where the inputs of the permanent memory blocks 4 and 5 are connected to the outputs of the counter for generating address 2, the outputs of the blocks for allocating the absolute value of signal 8 are connected to the inputs of the analog adder 9, the outputs of the loop counter 3 are connected to the inputs of circuit I 10, the input bus is connected to the analog inputs of the analog-to-digital multipliers 6, the initial conditions setting bus 12 is connected to the installation input of the address generation counter 2, with the installation input of the cycle counter 3, with analog input reset inputs tegrarators with a reset of 7, and to the output of circuit I 10 a signal bus 14 for completing calculations at a given frequency is connected, and also according to the invention contains k-2 read-only memory blocks 15 inserted into the device, where k is the total number of scanning sinusoidal signals in the device, connected in series with each of the k-2 blocks of read-only memory 15, analog-to-digital multipliers 16, analog integrators with a reset 17, blocks for extracting the absolute value of the signal 18, as well as an additional analog adder 19 and an output analog sum OR 20, where the inputs of the permanent memory blocks 15 are connected to the outputs of the counter for generating the address 2, the outputs of the blocks for allocating the absolute value of the signal 18 are connected to the inputs of the additional analog adder 19, and the outputs of the analog adder 9 and the additional analog adder 19 are connected to the inputs of the output analog adder 20, the input bus 11 is connected to the analog inputs of the analog-to-digital multipliers 16, the initial setting bus 12 is connected to the reset inputs of the analog integrators with reset 17, and the output bus 13 is sub yuchena output to the output of the analog adder 20.

, а блоки постоянной памяти 15 предназначены для хранения в цифровом виде и соответственно для выдачи в соответствии с формулами (2)-(4) последовательностей значений вспомогательных синусоидальных сигналов $$\sin (\omega t+\frac{\pi }{к})$$

и $$\sin (\omega t+\frac{\pi }{2}+\frac{\pi }{к})$$

соответственно на периоде T, где 0≤Т≤2π, $$\omega =\frac{2\pi }{T}$$

- циклическая частота, t - текущее время. Эти блоки имеют по n₁ входов, по m выходов, емкость по $$2^{n_1}$$

m - разрядных двоичных слов и реализуются на основе микросхем БИС ПЗУ. Аналого-цифровые умножители 6 и 16 реализуются на основе множительных цифроаналоговых преобразователей (ЦАП). Аналоговые интеграторы со сбросом 7 и 17, блоки выделения абсолютной величины сигнала 8 и 18, аналоговые сумматоры 9 и 19, а также выходной аналоговый сумматор 20 являются аналоговыми блоками и реализуются по одной из известных схем. Схема И предназначена для фиксации момента завершения формирования требуемого количества l последовательностей двоичных адресов с разрядностью n₁. При выработке требуемого количества последовательностей адресов (циклов) на счетчике циклов 3 формируется двоичный код, равный по величине требуемому количеству циклов. Единицы этого кода расположены в определенных и заранее известных разрядах, к которым изначально подключаются входы схемы И 10.An adjustable frequency clock generator 1 is a rectangular pulse generator of any known design with a frequency F adjustable in a given frequency range F ₁ ≤F≤F ₂ . Counters 2 and 3 are direct counters having n ₁ and n ₂ binary digits, respectively. Counter 2 is used to generate sequences of binary addresses with bit depth ni in the range of values from 00 ... 0 to 11 ... 1, and counter 3 is used to count the number of generated sequences of addresses in the mentioned range. The blocks of read-only memory 4 and 5 are intended for digital storage and, respectively, for issuing sequences of values of the main scanning sinusoidal signals sin (ωt) and $$\sin (\omega t+\frac{\pi }{2})$$

, and blocks of read-only memory 15 are intended for digital storage and, accordingly, for issuing in accordance with formulas (2) - (4) sequences of values of auxiliary sinusoidal signals $$\sin (\omega t+\frac{\pi }{\mathrm{to}})$$

and $$\sin (\omega t+\frac{\pi }{2}+\frac{\pi }{\mathrm{to}})$$

respectively, on the period T, where 0≤T≤2π, $$\omega =\frac{2\pi }{T}$$

- cyclic frequency, t - current time. These blocks have n ₁ inputs, m outputs, capacity $$2^{n_{\mathrm{one}}}$$

m - bit binary words and are implemented on the basis of chips LSI ROM. Analog-to-digital multipliers 6 and 16 are implemented on the basis of digital-to-analog converters (DACs). Analog integrators with a reset of 7 and 17, blocks extracting the absolute value of the signal 8 and 18, analog adders 9 and 19, and the output analog adder 20 are analog blocks and are implemented according to one of the known schemes. Scheme AND is intended to fix the moment of completion of the formation of the required number l of sequences of binary addresses with a bit length of n ₁ . When generating the required number of sequences of addresses (cycles), a binary code is generated on the cycle counter 3, which is equal in value to the required number of cycles. The units of this code are located in certain and previously known bits, to which the inputs of the And 10 circuit are initially connected.

, $$\sin (\omega t+\frac{\pi }{к})$$

и $$\sin (\omega t+\frac{\pi }{2}+\frac{\pi }{к})$$

на блоках постоянной памяти 4, 5 и 16 с заданной циклической частотой ω. Далее подается импульс на шину установки начальных условий 12, производящий сброс счетчика формирования адреса 2, счетчика циклов 3, аналоговых интеграторов со сбросом 7 и 17, и производится включение генератора тактовых импульсов 1. При включении генератора тактовых импульсов 1 на счетчике формирования адреса 2 последовательно во времени формируются n₁-разрядные двоичные адреса в диапазоне от 00…0 до 11…1. Количество циклов формирования адресов в указанном диапазоне подсчитывается счетчиком циклов 3. По сформированным на счетчике формирования адреса 2 адресам из блоков постоянной памяти 4, 5 и 15 выбираются хранящиеся в них значения базовых синусоидальных сканирующих сигналов sin(ωt) и $$\sin (\omega t+\frac{\pi }{2})$$

и в соответствии с формулами (2)-(4) значения вспомогательных синусоидальных сигналов $$\sin (\omega t+\frac{\pi }{к})$$

и $$\sin (\omega t+\frac{\pi }{2}+\frac{\pi }{к})$$

. На аналого-цифровых умножителях 6 и 16 формируются произведения f(t)·sin(ωt), $$f(t)\cdot \sin (\omega t+\frac{\pi }{2})$$

, $$f(t)\cdot \sin (\omega t+\frac{\pi }{к})$$

, $$f(t)\cdot \sin (\omega t+\frac{\pi }{2}+\frac{\pi }{к})$$

. На аналоговых интеграторах со сбросом 7 формируются интегралы $${\displaystyle \underset{0}{\overset{t}{\int }}f(t)\sin (\omega t)dt}$$

и $${\displaystyle \underset{0}{\overset{t}{\int }}f(t)}\sin (\omega t+\frac{\pi }{2})dt$$

.The device operates as follows. On the clock generator 1 with an adjustable frequency manually or using a microcomputer, the frequency F is set, which ensures the generation of signals sin (ωt) and $$\sin (\omega t+\frac{\pi }{2})$$

, $$\sin (\omega t+\frac{\pi }{\mathrm{to}})$$

and $$\sin (\omega t+\frac{\pi }{2}+\frac{\pi }{\mathrm{to}})$$

on blocks of permanent memory 4, 5 and 16 with a given cyclic frequency ω. Next, a pulse is sent to the initial setting bus 12, resetting the counter for generating address 2, the counter for cycles 3, analog integrators with resetting 7 and 17, and turning on the clock generator 1. When turning on the clock generator 1 on the counter for generating address 2 in sequence time, n ₁ -bit binary addresses are formed in the range from 00 ... 0 to 11 ... 1. The number of address generation cycles in the specified range is calculated by a cycle counter 3. Using the addresses generated on the address generation counter 2, from the read-only memory blocks 4, 5 and 15, the values of the basic sinusoidal scanning signals sin (ωt) and $$\sin (\omega t+\frac{\pi }{2})$$

and in accordance with formulas (2) - (4) the values of auxiliary sinusoidal signals $$\sin (\omega t+\frac{\pi }{\mathrm{to}})$$

and $$\sin (\omega t+\frac{\pi }{2}+\frac{\pi }{\mathrm{to}})$$

. The products f (t) · sin (ωt) are formed on analog-digital multipliers 6 and 16, $$f(t)\cdot \sin (\omega t+\frac{\pi }{2})$$

, $$f(t)\cdot \sin (\omega t+\frac{\pi }{\mathrm{to}})$$

, $$f(t)\cdot \sin (\omega t+\frac{\pi }{2}+\frac{\pi }{\mathrm{to}})$$

. On analog integrators with reset 7 integrals are formed $${\displaystyle \underset{0}{\overset{t}{\int }}f(t)\sin (\omega t)dt}$$

and $${\displaystyle \underset{0}{\overset{t}{\int }}f(t)}\sin (\omega t+\frac{\pi }{2})dt$$

.

и $${\displaystyle \underset{0}{\overset{t}{\int }}f(t)}\sin (\omega t+\frac{\pi }{2}+\frac{\pi }{к})dt$$

. На блоках выделения абсолютной величины сигнала 8 и 18 формируются модули интегралов. На аналоговых сумматорах 9, 19 и 20 вычисляется сумма этих модулей, величина которой в виде напряжения поступает на выходную шину 13. При завершении генерации на блоках постоянной памяти 4, 5 и 15 требуемого количества l периодов синусоидальных сигналов, где величина l, как отмечалось выше, вводится посредством соответствующего подключения входов схемы И 10 к выходам счетчика циклов 3, на сигнальную шину 14 завершения цикла вычислений при данной частоте ω с выхода схемы И 10 поступает сигнал. По этому сигналу производится считывание и соответственно запись величины выходного сигнала с шины 13 на соответствующее регистрирующее устройство. Величина считываемого выходного сигнала согласно (1) пропорциональна величине амплитуды А синусоидальной составляющей при исходно установленной циклической частоте ω. При работе в автоматическом режиме, т.е. при управлении работой устройства с помощью микроЭВМ, сигнал с сигнальной шины 14 о завершении цикла вычислений используется также для установки счетчиков и интеграторов устройства в начальное состояние и в качестве сигнала для микроЭВМ о формировании очередной частоты ω.On analog integrators with reset 17 integrals are formed $${\displaystyle \underset{0}{\overset{t}{\int }}f(t)}\sin (\omega t+\frac{\pi }{\mathrm{to}})dt$$

and $${\displaystyle \underset{0}{\overset{t}{\int }}f(t)}\sin (\omega t+\frac{\pi }{2}+\frac{\pi }{\mathrm{to}})dt$$

. Modules of integrals are formed on the blocks for extracting the absolute value of the signal 8 and 18. On analogue adders 9, 19 and 20, the sum of these modules is calculated, the value of which is supplied in the form of voltage to the output bus 13. Upon completion of generation on the permanent memory blocks 4, 5 and 15 of the required number l of periods of sinusoidal signals, where the value of l, as noted above , is entered by means of the corresponding connection of the inputs of the And 10 circuit to the outputs of the cycle counter 3, a signal is received from the output of the And 10 circuit to the signal bus 14 of the completion of the calculation cycle at a given frequency ω. This signal reads and accordingly records the magnitude of the output signal from bus 13 to the corresponding recording device. The value of the readout output signal according to (1) is proportional to the magnitude of the amplitude A of the sinusoidal component at the initially set cyclic frequency ω. When working in automatic mode, i.e. when controlling the operation of the device using a microcomputer, the signal from the signal bus 14 about the completion of the calculation cycle is also used to set the counters and integrators of the device to the initial state and as a signal for the microcomputer to generate the next frequency ω.

The effectiveness of the device in question can be illustrated by the following examples. The simulation directly showed [4] that when using two auxiliary scanning sinusoidal signals, i.e. when using formula (2), the relative error in determining the magnitudes of the amplitudes in the studied signals decreases to δ≈5%. When using four auxiliary scanning sinusoidal signals, i.e. when using formula (3), the relative error in determining the magnitudes of the amplitudes in the studied signals decreases to δ≈3%. When using six auxiliary scanning sinusoidal signals, i.e. when using formula (4), the relative error in determining the magnitudes of the amplitudes in the studied signals decreases to δ≈2%, i.e. decreases by about an order of magnitude.

 Information sources

1. Auto USSR No. 1812518.

2. RF patent No. 2018144.

3. RF patent No. 2404438.

4. Lyubomudrov A.A., Bashkov A.A. An approach to improving the accuracy of determining the amplitudes of sinusoidal components in the studied signals in spectral analysis. Proceedings of the scientific session of NRNU MEPhI-2010. In 6 volumes. Volume V. Information and telecommunication systems. Information Security Issues. M.: NRNU MEPhI, 2010.

Claims (1)

A device for analyzing signals in real time, containing a series-connected clock pulse generator with an adjustable frequency, an address generation counter, a cycle counter, two groups of nodes, each of which contains a permanent memory block, an analog-digital multiplier, an analog integrator with a reset and an absolute signal allocation unit, as well as an analog adder, AND circuit, input bus, output bus, initial condition setting bus, and cycle completion bus calculations, where the inputs of the permanent memory blocks are connected to the outputs of the address generation counter, the outputs of the absolute signal allocation blocks are connected to the inputs of the analog adder, the circuit inputs AND are connected to the outputs of the loop counter, the circuit output AND is connected to the bus to complete the calculation cycle, the input bus is connected to the analog inputs of analog-to-digital multipliers, the initial setting bus is connected to the installation inputs of the address generation counter, to the installation inputs of the cycle counter and to the analog reset inputs output integrators with a reset, characterized in that an additional k-2 groups of nodes are introduced into the device, each of which contains a sequentially connected read-only memory block, an analog-to-digital multiplier, an analog integrator with a reset and an absolute signal allocation block, where k is the total the number of scanning sinusoidal signals when performing spectral analysis, and also introduced an additional analog adder and an output analog adder, where the inputs of the blocks of constant the numbers are connected to the outputs of the address generation counter, the analog inputs of the analog-to-digital multipliers are connected to the input bus, the outputs of the absolute signal separation blocks are connected to the inputs of the additional analog adder, the outputs of the analog adder and the additional analog adder are connected to the inputs of the output analog adder, reset inputs of analog integrators with reset are connected to the initial setting conditions bus, and the output of the output analog adder is connected to the output bus.