SU1730639A1 - Device for determining correlation function measuring step - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to improve accuracy. The device contains a block 1 subtraction, adders 2, 14, filter averagers 3, 19, drivers 4,5 pulses, counters 6, 7, 16, elements 8, 13 delays, groups of elements And 9,10, registers 11, 12, block 15 calculating the approximation interval, 17 clock pulse generator, quadr 18, square root calculator 20, analog-to-digital converter. 1 il.

Description

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The invention relates to discrete automation and computing, can be used to determine the measurement step of the correlation function.

The purpose of the invention is to increase accuracy.

The drawing shows the electrical structure of the device.

The device contains a subtraction unit 1, an adder 2, a filter-averager 3, a formers 4, 5 pulses, counters 6, 7, a delay element 8, a group of elements AND 9, a group of elements AND 10, registers 11, 12, a element 13 of delay, adder 14, approximation interval calculation unit 15, executed as a constant memory block, counter 16, clock pulse generator 17, quad 18, filter average 19, square root calculator 20 and analog-to-digital converter (ADC) 21 .

The device works as follows.

After turning on the power, the counters 6, 7, 16 and the registers 11, 12 are set to the initial (zero) state, and the clock pulse generator 17 begins to generate clock pulses. At the same time, a random process realization arrives at the input of the device as the sum of the desired signal and interference. The implementation of the random process is applied to the first inputs of the subtractor 1 and the adder 2 and does not initially change in them, since the voltage at their second inputs corresponds to zero. Filter averager 3 performs averaging of the implementation of a random process and outputs a voltage of a centered implementation of a random process to the second inputs of subtraction unit 1 and adder 2. As a result, the output of the filter average 3 produces a voltage of a centered implementation of a random process that is transformed in the first shaper 5 pulses into a sequence of pulses corresponding to the intersection points of the zero level implementation. This sequence of pulses goes to the counting input of the first counter, where the pulse counting of the sequence takes place. At the output of the subtraction unit 1, a random process realization voltage appears displaced by the value specified by the averaging filter 3, which enters the input of the second pulse generator 4 and transforms therein into a sequence of pulses corresponding to the intersection points of the random process implementations by its mathematical waiting

The generated pulse train is fed to the counting input of counter 6, where it is counted.

When the clock pulses come from the 17 clock pulse generator to the counting input of the third counter 16, after some time it will overflow and again be reset to the zero state. The overflow signal from the output of the counter 16 is fed to the inputs of the installation in the zero state of registers 11 and 12 and confirms their zero state or translates them into this state. The same signal through the time interval defined by the delay element 13 enters the second inputs of the AND elements of the first 10 and second 9 groups and opens them for the time required to rewrite information from the potential single outputs of the trigger outputs of counters 6 and 7, respectively, to the pulse single inputs of the trigger registers 11 and 12. The signal from the second inputs of the AND elements of the first 10 and second 9 groups at an interval defined by the delay element 8 enters the reset inputs of counters 6 and 7, embeds them and thus prepares them for recording marketing information. In order to maintain the operation of the device, it is necessary that the delay of the signal by delay element 13 be somewhat longer than the zeroing time of registers 11 and 12, and the delay of the signal by delay element 8 should be slightly longer than the response time of the elements of the first 10 and second 9 groups.

Thus, the overflow signal from counter 16 connects the values of counters b and 7 to the inputs of the second adder 14, where these values are summed up, and the result of the summation goes to the information inputs of the block 15.

In addition, the signal from the output of subtraction unit 1, which corresponds to the current deviation of the input process from the average, is squared in the quadrant 18. Then, after averaging this signal in the average filter 19 and calculating the square root in block 20, an estimate of the standard deviation of the input process is formed but . This estimate is converted into a digital form in the ADC 21 and is fed to the input of block 15. The following values are entered at the address inputs of block 15:

the total value of the first and second counters (A + B), where A is the value of the first counter, B is the value of the second counter;

FT is the clock frequency;

N is the number of pulses required to overflow the counter 16;

 the estimated standard deviation (MSD) of the input process;

CBR is the coefficient taking into account the proportional relationship between the MSE and the upper frequency of the process.

As a result, block 15 calculates the measurement step of the correlation function using the formula

N kbrst

 - - - - - Ft (A + B) where r is the time after which it is necessary to measure the correlation function.

Claims (1)

Apparatus of the Invention A device for determining the step of measuring a correlation function, comprising a first filter averager, a first and a second pulse shaper, a clock pulse generator, three counters, two groups of AND elements, two delay elements, two registers, two adders, a subtractor and a calculation unit approximation interval, made in the form of a block of permanent memory, with the output of the first filter of the averager connected to the input of the first pulse shaper, the input of the decrementing block of the subtractor is information input device house, the output of the subtraction unit is connected to the first input of the first adder and through the second pulse shaper to the counting input of the first counter, the output of the first adder is connected to the input of the first average filter, the output of which is connected to the second input of the first adder and the input of the subtracted subtraction unit, the output of the first pulse generator connected to the counting input of the second counter, 0 five 0 five 0 five 0 the bit outputs of the first counter are connected to the first inputs of the corresponding elements AND of the first group, the outputs of which are connected to the corresponding bit inputs of the first register, the output of which is connected to the first input of the second adder, the second input of which is connected to the output of the second register, the bit inputs of which are connected to the outputs of the corresponding elements of the second group, the first inputs of which are connected to the corresponding discharge outputs of the second counter, the output of the clock generator is connected to the account the third input, the overflow output of which is connected to the reset inputs of the first and second registers and through the first delay element with the second inputs of the AND elements of the first and second groups, the output of the first delay element through the second delay element is connected to the reset inputs of the first and second counters, the output of the second the adder is connected to the first address input of the approximation interval calculating unit, the second address input of which is an input of the parameters of the measurement mode of the device, characterized in that No accuracy, it additionally includes a quad, a second filter averager, a square root computing unit and an analog-to-digital converter, the output and information input of which are connected respectively to the third address input of the approximation interval calculating unit and the output of the square root calculating unit, whose input is through the second the filter averager is connected to the output of the quad, the input of which is connected to the output of the subtraction unit.