SU1756883A1 - Finite field element multiplier - Google Patents

Abstract

The invention relates to computing, performs the operation of multiplying two elements of finite fields in one cycle of its operation and can be used in coding and decoding devices of binary codes operating with data as elements of different finite fields 2 m n GF (2) formed by various irreducible polynomials , where n is the boundary degree m of the extension of the field GF (2Sh). The aim of the invention is to expand the functionality of the device by ensuring that it performs the operation of multiplying the elements of arbitrary finite fields GF (2m) in one cycle. The device contains registers 1-4, block 5 of the formation of partial products, decoder 6, block 7 of forming lower coefficients, block 8 of forming higher coefficients, block 9 of forming degrees of primitive element, block 10 of equalizing coefficients, block 11 of the prohibition and block 12 summation. 3 hp ff, 9 ill. h y

Description

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The invention relates to computing, performs the operation of multiplying two elements of finite fields in one cycle of its operation, and can be used in coding and decoding devices of binary codes operating with data as elements of various finite fields.

2 m p

GF (2) formed by different

irreducible polynomials, where n is the boundary degree m of the extension of the field GF (2). The aim of the invention is to expand the functionality by ensuring the operation of multiplying the elements of arbitrary finite fields GF (2m), formed by various irreducible polynomials in a single cycle.

2 tons of p

works (where 2, n is the boundary (highest) expansion degree of the GF field (2), in which the multiplier of the elements of finite fields still performs the multiplication operation on the finite polynomial GF (2n); m is the expansion degree of the GF (2), with where the multiplier of elements of finite fields performs the operation of multiplying over the field of polynomials GF (2m), m 2,3 ... n; f (x) fmxm + fm-ixn 1 + ... + f0 is an irreducible parabolic term forming the field CG (2t).

FIG. 1 shows a functional diagram of a device for multiplying elements of finite fields; in fig. 2 is a unit for forming partial products; in fig. 3 - block forming the lowest coefficients; in fig. 4 — block1 of the highest generation coefficients; in fig. 5 is a functional block diagram of the formation of the degrees of the primitive element; in fig. 6 - block alignment factors; in fig. 7 - block prohibition; Fig. 8 is a functional diagram of the converter of the power generating unit of the primitive element; in fig. 9 - functional subblock signal conversion

The device for multiplying the elements of the final fields GF (2P) (Fig. 1) contains registers 1-4, block 5 of forming partial works, decoder 6, block 7 of forming lower coefficients, block 8 of forming higher coefficients, block 9 of forming degrees of primitive element, block 10 the alignment of coefficients, block 11 prohibition and block 12 summation.,

Block 5 of the formation of partial works (Fig. 2) contains n2 elements And 13, forming n groups 14 according to n elements And 13 each.

The unit of formation of lower coefficients (Fig. 3) contains n − 1 multiple input adders 15 modulo two. unit of formation of the highest coefficients

(Fig. 4) - p-2 multiple input adders 16 modulo two.

Block 9 (FIG. 5) contains a high-level signal source 17 and p-2 signal converters 18.

Block 10 alignment factors

(Fig. 6) contains n (n + 1) / 2) elements And 19 and (n-1) elements OR 20 with numbers of inputs equal to the numbers di n-l + 1, where I is the number of the element 20 OR in block 10 , I 1,2 ... p-1.

The prohibition block 11 (Fig. 7) contains (p-1) prohibition sub-blocks 21 and multiple-input adders 22 modulo two, an 18-signal converter (Fig. 8) of the block 9-n-1 of the keys 23 and p-1 of the conversion subunits 24.

A conversion subunit 24 (FIG. 9) contains a demultiplexer 25, an adder 26 modulo two, and a multiplexer 27.

The principle of operation of the device for multiplying elements of finite fields (Fig. 1) is based on the following mathematical relationships.

If a (x) am-ixm 1 + ... aix + a0 and b (x) bm-ixm + ... bix + bo the first and second elements of the polynomials GF (2) formed

by an irreducible polynomial f (x) fmxm + 4-fm-i xm 1 + ... fix + f0 with ax, where ai, bi, fi GF (2), a is a primitive element of the field GF (2m) and x is fictitious using to write field elements GF (2)

in the form of polynomials, the product c (x) of the first and second elements of the field GF (2m) is calculated by the formula:

 b (x modHxHa 1. (xm-ft ..,

v go- L v, L .1 g.

-P (lt .. t

2 (,

- (L Sapbl

go

-, 2 (w «),

 V. / V. J w V iV MILAyy jA.I,

k, xw- (T ... + + b0)

/ 2 (rn - (), ..

 2 (Z4bJx mo №l T o

tn- ,, 2ta}, ..

S 2.a, i,) v + z 2 AI "

 vp + i j-№xp + (j

mi, 2 (“- 0

"HW-Zz.vjxvz: s.apb, c (.

v oVp + (; i g r

We introduce the notation:

55 ki apbq, where I 0,1,2, ... m-1. - youngP + qi are the highest product coefficients;

kj X apbq, where j m, m + 1, ... 2 (m-1), p + q J

higher product coefficients. Then

m - 1 2 (m - 1)

c (x) 2 kix + 2 J "cm-ix1 ™ -) -...

I 0j m

... + C1X + Co.

Registers 1-3 receive, store and issue the coefficients ai, bi, fi, respectively. In register 4, the binary representation of the number m (the degree of expansion of the polynomials GF (2m), on which the multiplication is carried out) is received, stored and issued.

In block 5, pairwise multiplication of ar bq is performed over the field GF (2) of all coefficients of the first and second factors, respectively.

In the decoder 6, a high level signal is produced at the mth output to the corresponding binary representation of the number m.

In blocks 7 and 8, signals are generated that correspond to ki and higher kj product coefficients.

In block 9, signals are formed at its outputs corresponding to the powers of the primitive field element

d.

In block 10, signals are generated at its outputs that correspond to signals in its first group of inputs shifted by n-m outputs towards the outputs with lower numbers.

In block 11 of the prohibition, signals are generated at its outputs, Co2 (T-1)

corresponding to the sum of 2 B block 12

j m

the formation at its outputs of signals corresponding to the coefficients ct of the product is carried out.

When describing the principle of operation of a device for multiplying elements of finite fields (Fig. 1), it is necessary to take into account that the high level of the signal at the input or output of a functional element or device determines the true value of the value, and a low level determines the false value.

In addition, the unit in the binary representation of a number corresponds to a high-level signal at the corresponding input or output, and zero to a low level and vice versa, a high-level signal at any input or output corresponds to one in the binary representation of the corresponding number, and a low level to zero.

A device for multiplying elements of finite fields works as follows.

Procedure 1.

In the initial state of the device, the inputs of the coefficients of the first and second factors, the inputs of the coefficients of the non-reducible polynomial and the inputs of the degree m of the expansion field, and thus the information inputs of the registers 1-4, are low-level signals. In addition, registers 1-4 are reset to zero-zero by applying high-level impulse signals to the first and second inputs of the device reset, then low-level signals are sent to the first and second inputs of the device reset, 0 At the outputs of all registers 1 -4 signals of low levels are formed, and therefore, signals of low levels are also formed at all outputs of the first and second groups of outputs of block 5 of the formation of partial works at the outputs of blocks 7, 10 and 11, which, in turn, leads to the formation of signals neither zky levels at the outputs of the device of the coefficients of the result. 0 Procedure 2.

Before starting the device, the device of elements of finite fields is set up on the field GF (2m), whose elements

the device will multiply. 5 This setting is performed by applying a pulse signal to the second input of the device, and then feeding to each 1st device input (I 1.2p-1) the coefficients of the irreducible polynomial 0 of the pulse signal corresponding to the coefficient f |, and to the inputs of the device of degree m the field - the pulse signals corresponding to the binary representation of the number m, with the j-th input 0

5 1, (+1)) corresponds to the j-th

bit of the binary representation of the number m. In addition, on the i-th output of register 3 and on the j-th output of register 4, for which fi and j-th bit of the binary representation 0 of the number m are equal to one, high-level signals are formed, respectively.

Hence, at the m-th output of the decoder 6, at the m-th input of the second group of inputs of block 10 and at the (t-1) -th input (with m 1) of the second 5 groups of inputs of block 9, a high level signal is generated. At the outputs of block 9 and, therefore, signals are formed on the second group of inputs of block 11, depending on the signals on the first and second groups of inputs of block 9

achhri

in accordance with the principle of operation of block 9.

Procedure 3.

To perform the multiplication of elements

m -1

of the final floor GF (2m) a (x) Ј

t -1

B (x) 2 / bqxq necessary for each

(pn-And + p) -th input of the device of the coefficients of the first factor and for each (qM) -tf input of the device of the coefficients of the second factor send pulsed signals corresponding to the coefficients ap and bq, respectively, and to the other inputs of the device to give signals of low levels . At the same time, at (n-m + 1 + p) -th outputs of register 1 and (g + 1) -th outputs of register 2, for which ap and bq are equal to one, high-level signals are formed, respectively.

Further, at the outputs of blocks 5, 7, 8, 10, 11 and 12, signals are formed that correspond to the logic of their operation.

Procedure 4.

In order for the device to perform the operation of multiplying the elements of the same GF field (2m) to which the device is configured, you must first reset registers 1 and 2 to the zero state by applying pulse signals to the device’s first reset input, and then performing procedure 3.

Procedure 5.

In order for the device to perform the operation of multiplying the elements of another field, other than the field on which the device performed the operations of multiplication, it is necessary to perform procedures 2 and 3.

Claims (1)

Invention Formula 1. A device for multiplying the elements of the final fields GF (2n) containing the first and second n-bit registers, the partial product formation unit and the summation unit, the outputs of which are connected to the outputs of the device's product coefficients, the inputs of the coefficients of the first and second factors of which are connected respectively to information inputs of the first and second n-bit registers, the outputs of which are connected to the corresponding inputs of the unit for the formation of partial products, which is characterized by the fact that, in order to expand functional capabilities due to the operation of multiplying arbitrary finite fields GF (2m) (where 2Јt n) formed by various irreducible polynomials in one work cycle, the third (n-1) -sized register is entered into it, the fourth (1 Iog2 (n +1) the bit register, the decoder, the unit for forming the degrees of the primitive element, the units for forming the higher and lower coefficients of the product, the unit for equalizing the coefficients and the prohibition unit, the outputs of which are connected to the inputs of the first 0 group of the summation unit, the inputs of the second group of which are connected to the outputs of the coefficient equalization unit, the inputs of the first group of which are connected to the outputs of the formation unit of lower coefficient of product whose inputs are connected to the outputs of the first group of outputs of the partial product formation unit, the outputs of the second group of which are connected to the inputs block formation 0 senior product coefficients, the outputs of which are connected to the inputs of the first group of the prohibition block, the inputs of the second group of which are connected to the outputs of the power generation unit of the primitive element, the inputs of the first group of which are connected to the outputs of the third (p-1) -bit register, information the inputs of which are connected to the inputs of the coefficients of the irreducible polynomial of the device, 0 inputs of degree m expansion of the floor of which are connected to information inputs of the fourth (3 Iog2 (n + 1) C) -resignal register, the outputs of which are connected to the inputs of the decoder, the outputs of which 5 are connected to the inputs of the second group of the coefficient equalization unit and the power generation unit of the primitive element, the reset inputs of the first and second n-bit registers are connected to the first device reset input, the second reset input of which is connected to input- & 1) -discharge and fourth (3 loga (n + 1)) -discharge registers. 5 2, device pop. 1, characterized in that the unit for forming the degrees of the primitive element contains a source of a high level signal and (n-2) signal converters, with the jth inputs of the first group () of each 1st  signal converters (1 1п-2) and j inputs (n-2) of the signal converter are connected to the corresponding outputs of the block, the inputs of the first group of which are connected to the inputs of the second group of each j-ro signal converter and) the inputs of the first group of the first signal converter , the first input of the first group of which is connected to the output of a high-level signal source, the inputs of the second group of the block are connected to the inputs of the third group of each 1st signal converter, the outputs of the 1st signal converter are connected to the inputs of the first group nN (1 + 1) th transducer signals ((p-3)). 3. The device according to claim 2, that is to say that each signal converter contains (p-1) keys and (p-1) sub-blocks of signal conversion, the outputs of all the keys and the first inputs of all the signal conversion subunits are combined and connected to the first output of the signal converter, (p-1) of the following outputs of which are connected respectively to the outputs (p-1) of the signal conversion sub-blocks, the second inputs of which and the information input of the (n-1) -th switch are connected to the corresponding the inputs of the first group of signal converter, the third inputs are all ex subblocks of the signal converter are connected to the inputs of the second group of signal converter, the inputs of the third group of which connected to the control inputs of the corresponding keys, the information input of the 1st key is connected to the (1 + 1) input of the first group of signal converter 4. The device according to claim 3, wherein it is each that a signal conversion subunit contains a demultiplexer, a modulo two adder and a multiplexer, the output of which is connected to the output of the signal conversion subunit, the first input of which is connected with the first input of the modulo two adder, the second input of which is connected to the first output of the demultiplexer, whose information input is connected to the second input of the sub-unit of signal conversion, the third input of which is connected to the control inputs of the demultiplexer and multiplexer, The first and second information inputs of which are connected respectively to the output of the adder modulo two and the second output of the demultiplexer. P FIG. 2 6 p-1 P / g shhhhh and 21 P 21 w Fie.7 Fig 8 25 27