SU1598200A1 - Device for digital shaping of amplitude-phase modulated signals - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to improve the accuracy of the formation of signals. The device contains data source 1, encoder 2, delay blocks 3-6, multiplexer 7, memory block 8, buffer register 9, adder 10, register 11, key 12, D / A converter 13, filter 14, control block 15, block 16 forming addresses and speed switch 17. The binary sequence from source 1 enters encoder 2, which in three stages recodes it into four sequences. From these, blocks 3–6 delays further form four binary bit words that go to multiplexer 7. It alternately switches each word to the output, which goes to memory block 8. At its outputs, alternately multi-digit numbers appear that are fed to the adder 10 directly and through the register 9 with a shift of one bit to the left. Next, the numbers are written to register 11 and through the key 12 are fed to the D / A converter 13, which converts the numbers into samples of the analog signal. Filter 14 then filters the conversion by-products into them. Given il. performing encoder 2, control unit 15, and generation unit 16. 3 il.

Description

The invention relates to communication technology and can be used in data transmission systems over primary broadband communication channels.

The purpose of the invention is to improve the formation accuracy.

FIG. depicts a structural electrical circuit of the proposed device; in fig. 2 is a diagram of the encoder of FIG. 3 is a circuit of a control unit and an address generation unit.

The device contains a data source 1, encoder 2, blocks 3-6, delays, multiplexer 7, memory block 8, buffer register 9, adder 10 register 11, key 12, digital-to-analog converter 13, filter, control block 15, address generation block 1b , switch 17 speed work.

Encoder 2 consists of shift registers 18–20, modulo two adders 21–28, and buffer register 29.

The control unit 15 consists of counters-dividers 30 and 31, a decoder 32, elements HE 33-35, element AND-HE 36, one-shot 37.

Block 16 consists of counters 38 and 39, element 0, and a persistent storage device tl.

The device works as follows.

The binary sequence from the output of source 1 comes at a speed Vg to the input of encoder 2, which transcodes it into four sequences, C, ic, the V following speed is four times lower than the speed of the original sequence la following the recoding process was carried out in three stages. At the first stage, four sequences are formed from the initial sequence a.) I, d.ji by the rule

4k (-l ® 4k- "dikfl 1-k + i ® ® dfUi af (s ® .j

1,2,3 ... (1)

 The operation is carried out by means of a delay element for twelve clock intervals (registers 18-20 and four adders 21-2). This

the operation is necessary to eliminate the error multiplication phenomenon, where the symbol f denotes modulo two. At the second stage, each odd element of the subsequences is inverted.

, (what is needed to form a signal with amplitude-phase modulation and one sideband, this results in four subsequences

15

ь;, ь ь;}, c, ed,

0

where b ((-1)

b (-d 4) -g (1)

 4k + 1 (-)

with;; rk .. (-1)

1,2,3 .. (2)

Each of the sequences is inverted using adders 25-28, to one input of which the symbols of one of the sequences are fed, and to the other input - a control signal (1). If the value of the control signal is a logical one, then the symbol of the subsequence is inverted, if the logical zero, is transmitted without change. At the third stage, the received characters of the subsequences 1y, b, c are written into the buffer register 29. Four characters of the subsequences, for example, b. . B {, c |, c are stored in it until the following four values appear on its inputs:

((. "I k- f °

For normal clock operation

0

45

50

the encoder inputs from block 15 are supplied, frequencies F :, FT /,, F /.

It should be noted that in this case a multi-level signal is formed with amplitude-phase modulation and one sideband by obtaining the values of the in-phase (b) and quadrature C envelopes. The values of quadrature envelopes are associated with the sequences L |,, and C,

with as follows: k

 b 2b Ci + 2C

k

/ f

(with

(3)

55

where b / b, b, c, c j can take the values ± 1 and so are binary symbols, and c} and b c

51598200

can take the values ± 1, t3 and represent four-level symbols.

From the output of the encoder 2 characters of the subsequences (,,, Gs come respectively on the input N -1

3-D dixie blsekov. The number of taps in each of the delay is 2N. The delay block itself is a sequential shift register. At the outputs of the delay blocks, for example, block 3, a binary 2N bit word is formed, the characters of which are, respectively, b.

gd

would

ten

b.

kn kn

..., Dj, o f ...,. The information on the outputs of the delay lines 4-6 is formed in a similar way from the subsequences fb / L fci ,,

p; s Four binary 2N bit words from the outputs of blocks 3 and 6 are received simultaneously at the inputs of multiplexer 7. At the control input of the multiplexer, a two-bit word can be supplied from block 15, which can have four. values 00, 01, 10, 11. At the same time depending on the value of the control word at the output of multiplexer 7 one of four 2N-bit words generated at the outputs of blocks 3 and 6 is switched. In a manner, at the output of multiplexer 7 each of the words obtained at the outputs of blocks 3-6, appears alternately through one quarter of the period of the average frequency of the spectrum being formed (Pcp).

From the output of the multiplexer 7 2Y-, the spread words are fed to the lower bits of the address of the inputs of block 8. Block 8 stores pre-calculated samples of the output signal of the low-pass shaping filter (LPF), which are a convolution of the impulse response of the LPF with the binary information sequence . The signal at the output of the low-pass filter with impulse response) of a finite duration when a synchronous sequence is applied to its input, for example bj), is described by the well-known expression

15

20

yes ph o c chi

ra

25

30 v

,, where

40

to

45

50

Where

R

i Oh 1,2,3 .. oh

be found from (a) as b (iC) b.i (

- (r + k) t).

ten

15

Usually in real data transmission systems the value of the average frequency of the formed spectrum F and the speed of the following V are related as primes.

one

n -, i.e.

ha

  i. (6)

20

Taking this circumstance into account, expression (5) can be written as

N-1

Zb

h (i i T m

25

- (r + k) t).

(7)

n

Expression i 1 as a sum of two components

1 - T will be presented in m

i CT + i T,

m

(eight)

,, where K is a whole part of dividing the number

. ,, V1

(in) by m, and - is the remainder of

40

dividing the number (in) by m, 1 0.1.2, ..., m-1. Then the expression (7) is converted

to mind

Bd-) v (kt + - t)

m

m 5: h, h (KT

Yy-n

N-f

-yr-qt) b y .-. (

ITm

, m4t-gt). (9)

B (t)

N-1

 - (r + k) Tj. (A)

It can be seen from expression (9) that the samples of the signal at the output of the low-pass filter taken at moments iC can take a finite set of values, which is defined by where T is the duration of the input unit of the length of the delay line 2N and the numerical pulse. In this case, the signal counts for all

scrap m, depending on the ratio of the scf low pass filter at time points

t iC,

the growth rate of V and the average frequency of the spectrum. Number of possible

Scrap, depending on the ratio of the speed of following V and the average frequency of the spectrum. Number of possible

the values of the samples of the signals B (it) - is M 2, since you take only one of the two values +1 or -1, and 1 O, 1, ..., t-1. Therefore, it is possible to calculate in advance with high precision all M possible values of SI1 of Bala (ic) and write them into a memory block. Then, when generating the next value of B (i t) F (b | (, b +1, bj, b,), it suffices to apply a binary to the address inputs of the memory block.

the word fbj, ..., bj; ,, b J ,,,

f binary word 1.

Thus, two-bit binary words appearing on: output of multiplexer 7 are served to the lower bits of the address inputs of memory block 8, to the high bits of which address inputs of binary inputs 1 are supplied from the output of block 16.

As a result, the outputs of block 8 alternately appear multi-digit numbers B ,, B, C, C, where

  , f-n

(ten)

The numbers B, B, C, C., From the output of block 8 are fed to the input of the adder 10 and the input of the buffer register 9, and to the input of the adder 10 these numbers are shifted one digit to the left. A write signal is sent to the clock input of the buffer register 9 of block 15 at the instants of occurrence of the numbers B,, and C, therefore the number B is written to the buffer register 9 and fed to c. delaying the second input of the adder 10. At the time when the first 10 input of the number B is entered (with a shift by one bit), a number B is formed at its outputs equal to

B T + 2B J..

This number in is written to register 11. Then, from block 8, the number C is fed to the input of buffer register 9, written to it and fed with a delay to the second adder 10, where

five

five

0

five

0

0

is given with the number C. As a result, the number C appears at the outputs of the adder 10

С С + 2С.

The number C is also recorded in register 11. Register 11 is necessary to delay the number B of the fourth period of the Fcp frequency. Register output

11 is connected to the key input 12. Key

12, in accordance with the control signal from block 15, supplies the digital-to-analog converter 13 first with the number B., then after one quarter of the period of the frequency F cf the number C, then after the period of the frequency Fj.p the next

number B

+

etc. The duration of the filing of numbers on the digital-to-analog converter 13 does not exceed 200-300 n. The digital-to-analog converter 13 converts the numbers B and C into samples of an analog signal with a duration of 200-300 NS. The output of the digital-to-analog converter 13 is connected to the input of the filter 1, which filters out

conversion byproducts. I

When transmitting on a primary uw-band link, a number of standard speeds are used. The specific transfer rate is selected by switch 17, which supplies the block 16 with a two-bit word: 00, 01, 10, 11, which determines which of the following speeds V is used: 2k. 32, 38 or V kBaud. The same word is fed to a frequency synthesizer (not shown), from which one of the four FT- clock frequencies is supplied to block 15: EB, 128, 14, or 192 kHz and the control frequency is equal to b72 kHz. The address forming unit 1b consists of a serially connected counter, to the input of which the frequency F is applied, is equal to kHz, from block 15 and the outputs appear from O to t-1 (in this case 21), and devices. A two-word word from the output of the switch 1 7 and a signal from the block 15, which determines how much output is output from the block 16. The block 15 ensures the coordinated operation of all the blocks of the device.

Claims (1)

DETAILED DESCRIPTION A device for digitally generating signals with amplitude-phase modulation and one sideband, containing a data source, first and second delay blocks, a memory block, an adder, a D / A converter, the output of which is connected to a filter input whose output is output Devices, characterized in that, in order to improve the shaping accuracy, an encoder, a third and fourth delay blocks, a control unit, a multiplexer, an operation speed switch, an address generation unit, a buffer are introduced. register, register and key, with the source output connected to the input of the encoder, the outputs of which through the corresponding delay blocks are connected to the inputs of the multiplexer, the output of which is connected to the lower bits of the address inputs of the memory block tj, the output of which is connected to the input of the buffer register and the first input of the adder, the output of which through the serially connected register and the key is connected to the input of the digital-analogue converter, the output of the operation speed switch is connected to the input of the address generation unit, the output of which is connected to the upper bits of the address inputs the memory block, the output of the buffer register is connected to the second input of the adder, the outputs of the control unit are connected respectively to the clock input of the encoder, clock inputs of the delay blocks, control l yuschim input of the multiplexer, a clock input buffer re17ist- pa clock input of the register, a control input of a key, a control input address generating unit, the control unit inputs are the control and clock inputs. From, Bl / 7-H J ag.Z