SU1751769A1 - Conveyer buffer storage for systems of image processing - Google Patents

Description

the device, the address switch output is connected to the address input of the data memory, the address input and the data input of the address memory are connected to the bits of the first and second coordinates of the input to the full address of the device fragment, the output of the data memory is information output of the device the output of the address translation block is the address output of the device, the memory block of the output address queue is entered, the memory block of the input address queue, the memory block of the data queue, the memory block of the address of the data fragments, the first the data block input address of the data fragments and bits of the first control input of the memory block of the output address queue are connected to the lower bits of the first and second coordinates of the input of the full address of the device fragment, the second output of the address conversion block is connected to the information input of the memory queue of the input the address, the output of which is connected to the first information input of the address switch, the first control input of the memory block of the output address queue is connected to the write enable input of the address memory block, The first and second information outputs of which are connected respectively to the first and second information inputs of the memory block of the output address queue, the second and third control outputs of the memory block of the output address queue are connected to the third and fourth control inputs of the address conversion block whose information input is connected to the first information output of the memory block of the output address queue, the strobe inputs of the recording of the memory block of the data fragment addresses, the memory block of the address and the memory block of the output queue The address of the device is combined and connected to the strobe input of the entry address of the device, the overflow output of the block of addresses of data fragments is the output of prohibiting the write of the device, the second information output of the block of the output address queue memory is connected to the second information input of the block of addresses data fragments, the eighth and ninth outputs of the control unit are connected to the second and third control inputs of the memory block of the output address queue, the second and third inputs of the control unit are connected to the fourth and the fifth control outputs of the memory block of the output address queue; the fourth and fifth inputs of the control block are connected to the data readiness and data overflow output

the data queue memory block, respectively, the data unload input and the data queue memory block data input are connected to the tenth and eleventh outputs of the control unit, the information input of the data queue memory block is the information input of the device, the output of the block is connected to the information input of the memory block these data, the twelfth and

0 the thirteenth outputs of the control unit are connected to the inputs for loading and unloading data of the memory block of the input address queue, the fourteenth output of the control unit is connected to the input of data unloading of the block

5 memory addresses of data fragments, the first and second information outputs of the memory of addresses of data fragments are connected respectively to the second information input of the switch and to the information input of the control unit, the sixth input of which is connected to the output of readiness of the output data of the memory block of addresses of data fragments.

The output address queue memory block

5 contains a node for masking and cyclic shift of comparison flags, a flag register, an encoder and a decoder, a queue memory node, a unit counter, the first information input of the block connected to

0 the first information input of the queue memory node, the first information output of which is the first information output of the block, the second information output of the queue memory node

5 is connected to the data input of the flag register, the output of the flag register is connected to the input of the encoder, the first output of which is connected to the fifth control output of the block, the second and third outputs of the encoder are 0 to the second and third control outputs of the block, respectively, and connected to the information decoder input whose gating input is the third control input of the unit, the first

5, the control and second information inputs of the block are connected to the control and information inputs of the masking and cyclic shift node of the comparison flags, the first output of which is connected to

0, the second information input of the queue memory node and the input of the unit counter, the second output of the masking node and the cyclic shift of the comparison flags is the first control output of the block, the decoder outputs are connected to the flag register reset inputs, the output of the queue memory node is connected to the gate input the flag register is the fourth control output of the block; the unloading input of the queue memory node is the second control input of the block; the first output of the unit counter is connected to the write enable input of the node n m five turns, the second output is a second data output unit, the entrance gating recording memory queue node connected to the input of the input gating recording device address.

Figure 1 shows a functional diagram of a conveyor buffer storage for image processing systems; Fig. 2 is a functional block diagram of an output address queue; FIG. 3 shows an address translation unit; 4 (a) is a memory block of addresses of data fragments; 4 (6) -block memory block; figure 5 - block diagram of the algorithm for loading data; figure 6 is a block diagram of the algorithm for unloading data; Fig. 7 shows an address memory block; Fig. 8 shows a masking and cyclic shift node; Fig. 9 illustrates a data storage unit; figure 10 is a node of the cyclic shift of the output data.

The buffer memory (Fig. 1) contains an address memory block 1, an output address memory block 2, an address conversion block 3, an address switch 4, a data memory block 5, a data queue memory block 6, a control device 7, block 8 of addresses of data fragments, block 9 of memory of a queue of input address, fragment gate addressing line 10, full fragment address bus 11, data recording prohibition line 12, data output bus 13, output data line 14, address output bus 15, segment address readiness line 16, readiness line 17 and input data, input data bus 18, first 19 and second 20 information outputs of the address memory block, first control output 21, second vm-formation output 22. second 23 and third 24 control outputs, first information output 25 of the output queue memory block addresses, eighth 26th and ninth 27 control outputs of the control unit, fourth 28 and fifth 29 control outputs of the output address queue memory unit, third 30 and fourth 31 control outputs of the control unit, second output 32 of the address translation unit, first 33 and second 34 information th outputs, control output 35 of the memory block of data fragments, seventh 36, first 37, second 38, tenth 39 and elevenG 40 control outputs of the control block, fourth 41 and fifth 42 inputs of the control block, switch output 43, output 44 data of the data queue memory block, the twelfth 45 and thirteenth 46 outputs of the control unit, the output 47 of the memory block of the input address queue, the fourteenth control output 48 of the control unit.

The next output signal memory block contains a queue memory node 49, a comparison flag register 50, a priority encoder 51, a decoder 52, a masking and cyclic shift node 53, a 54 unit counter, a first counter output 55 units, a first masking and cyclic shift node output 56 , the second information output 57 of the queue memory node.

The address translation unit comprises the first 58 and second 59 address adders, the address increment adder 60, the switch 61, the shift register 62, the string length register 63.

The address memory block contains four groups of address adders 64, four memory modules 65, four comparison circuits 66, addresses and data in memory modules 65.

The node 53 masking and cyclic shift of the comparison flags contains the first and second shift input circuits 67 and 6C of the first cascade, the input shift circuit 69 of the second cascade, the output circuit 70 of the shift of the first cascade, the first and second output circuits 71 and 72 of the second shift, elements And 73-76, elements NOT 77 and 78, elements OR 79 and 80..

Data memory block 5 contains sixteen groups of adders 81 addresses, sixteen memory modules 82, cyclic shift node 83 of the output data with inputs 84.

Node 83 cyclic shift output data contains four schemes 85 shift of the first stage and group scheme 86 shift of the second stage.

Conveyor buffer storage device operates as follows.

Input 11 receives P bits, where P Iog2 M + Iog2 N, specifying the full address of the element of a two-dimensional data matrix of dimension MxN, the address inputs of block 1 receive bits mi of the first coordinate,

where 1 1 ioga M-1, and bits of the second

coordinates, where 1 1toga N-1, at first

the information input of block 8 receives the lower bits of the first coordinate,

where i 0loQ2 L-1, and the younger bits u

the second coordinate, where i 0 Iog2 K-1,

moreover, the capacity of the data memory block 5 is (LxK) elements. The first control input of block 2 receives the bits mo, mi, gp2 and Po, ni. A2 full address of the fragment.

Before starting work on the initial setup signal, all the memory cells of the address block 1 are reset,

erasing the contents of blocks 6, 8, 9, 49. The outputs 12.42 of blocks 8 and b are set to one state - the resolution of data recording. Outputs 35, 28. 41 blocks 8, 49 and b take a zero value, meaning no loaded data. The control device 7 enters the state corresponding to the point A of the algorithms in FIGS. 5 and 6. Operator 1 (FIG. 5) checks the signal on line 29, which is an indicator of data loading in block 49. Operator 1 (FIG. 6) checks the signal on line 35 of the control output of block 8. In the absence of data in blocks 8 and 50, the control unit cyclically performs operations 1 in FIGS. 5 and 6. The algorithms in FIGS. 6 and 5 are executed in parallel and are not interconnected .

The external driver sets the address of a two-dimensional fragment at input 11 and after a period of time t generates a gating pulse on line 10. Junior bits and total bits mi and m arrive at adders 64 (Fig. 7) of each of the four memory modules 65. memory addresses. At the outputs of the adders, the full addresses of the four segments are set in which the fragment elements (1) can be located. In comparison schemes 66, the high-order bits of the full address of the segment are compared with the data in the corresponding memory module, addressed by the lower-order bits of the full segment address. The bits of the four-bit output 20 of block 1 (comparison flags) to restore the order of flags, distorted by using the function of distributing data across memory modules, go to the first and second input circuits 67 and 68 of the first stage of block 53, and then on the output circuit 69 of the shift of the first cascade. In circuits 67 and 68, controlled by bit y, 2 full memory addresses, a cyclic shift is performed within flag groups, two in each group, in the second stage (circuit 69). controllable P2 of the full memory address, a cyclic shift of groups To arrange an arbitrary sample of a fragment from block 5, one to four segments need to be loaded, which is determined by the position of the 3-D element inside the fragment. Therefore, the four-bit code of the comparison features, after adjusting the position of the data, enters the masking scheme, which is implemented on the base of elements 72-80. The masking scheme prohibits the selection of unnecessary segments from the memory of the original image. The masking of comparison flags is done by

bits m0, mi, n0, ni full memory address. The outputs of the masking and cyclic shift node 53 are two four-bit outputs: write enable signals to the memory modules of block 1 (output 21) and comparison flags modified by the masking circuit (output 56). In order to correctly write to the memory modules of block 1 of the highest bits of the addresses of the segments in shear patterns 70, 71, 72 of the shift (Fig. 8), the position of the bits and codes of the comparison flags is inversely corrected. In circuit 70, controlled by the bit resolution gp2 of the full memory address, the position of two groups of

5 two bits of the flag code, in circuits 71 and 72 controlled by bit P2, the position of the bits within groups is changed.

During the time t, the output 19 of the block 1 forms the address of the base segment, the output

0 four-bit bus 20 — indications of the presence of the required data segments in the memory unit 5. The bit values of the bus 20 arrive at the information input of the node 53 of masking and cyclic shift of the comparison flags. Under the control of the bits mo, mi, gp2 and n0, ni, bus 11 of the complete fragment address, a four-bit code 56 of the comparison flags and signals 21 of the write resolution to the memory modules of block 1 are generated at the first output of node 53. Values of signals on bus 56 arrive at the second information input of the queue memory unit 49 and at the inputs of the 54 unit counter, which is a combination logic circuit. At the outputs of the counter 22, a binary position code is generated, the value of which is determined by the number of units on the 56 bus. The counter includes an OR circuit. entrances which

0 is connected to the bus bits 56, and the output is counter output 55. If at least one of the bits of the bus 56 is set to one, then the output 55 of the block 54 is set to a single state and allows

5 load the base segment and the code of the comparison flags in memory block 49.

After all signals have been installed, the external master device with a gating pulse on line 10 loads the values

0 senior bits of addresses of the requested segments in the memory modules of block 1. The value of the base segment on bus 19 and the code of comparison flags are not on bus 56 in memory block 49 of the queue, the value of the lower bits of the first and second coordinates of the full fragment address and the output value of the counter units on bus 23 into block 8 of memory addresses of data fragments. After that, the external driver checks the output value 12 of the address memory.

data fragments. If the memory block is not full, then the download of the new fragment is repeated. If output 12 goes to the state O, which means that the memory is full, the loading stops.

When data is loaded into memory unit 49, output 28 is set to 1. A positive front of which loads the output code value of the comparison flags at output 49 of the register 50 of flags. The priority encoder 51 includes an OR circuit whose inputs are connected to the outputs of the flag register and the output is line 29. On line 29 is set to 1. The operation algorithm of the control device when loading data into the buffer memory is presented in FIG. After the initial installation, the control unit performs a cyclic check of the state of line 28 (algorithm block 5-1), and if it is set to one, analyzes the state of line 29 (algorithm block 5-2). If line 29 is set to one, the control unit cyclically checks the status of line 42 to ensure that the data queue memory 6 is ready to receive data (algorithm block 5-3). If block 6 is not filled, line 42 is set to one. In this case, the control unit switches the address switch 61 by signal 30 so that the outputs of adders 59 and 58 are connected to the inputs of register 62 (algorithm block 5-4), gates the address of the first loaded segment into the output address register 62 by a signal on line 31 (algorithm block 5-5), generates a request for the memory of the original image on line 16 (algorithm block 5-6), loads the minor address address of the segment on bus 32 into block 9 of the input address queue signal on line 45 (block al Oritma 5-7).

The address of the loadable segment contained in register 62 is formed from the address of the base segment bi j generated in address memory block 1 The full address of the base segment on bus 25, divided into addresses on the first coordinate and addresses on the second coordinate, is connected to the first inputs respectively of adders 58 and 59. The full address of the segment from the output of the adders through the switch 61 is fed to the bypass of register 62. The outputs of the register of 50 flags are connected to the inputs of the priority encoder in the following order of decreasing priority: the segment flag bi-i, ji, the flag seg cient bi.j-1, bj-i flag segment 1, the segment flag bi, j, Accordingly codes generated for each priority encoder flag is yuschegos senior at some point in time,

the following: 11, 10, 01, 00. The most significant bit of the output code of the priority encoder is input to the subtraction input of the unit of the adder 58, and the low order to the input of the subtraction

units of adder 59.

After setting the segment address in register 62 and requesting the memory of the original image on line 16, control unit 7 analyzes the state of data readiness line 17 (algorithm block 5-8). When the true data is installed at the input 18, which is accompanied by a change in the state of the line 17, the control unit 7 generates a data recording strobe on the line

5 40 to block 6 of the data queue memory (algorithm block 5-9). Next, the control unit removes the truth signal of the data on line 16 (algorithm block 5-10) and gates the outputs of the decoder 52 with a signal on the line

0 27 (algorithm block 5-11). On the falling edge of this pulse, the flag in the register 50 corresponding to the loaded segment is reset. After that, the control device analyzes the state

5 lines 29 (algorithm block 5-12). If in the register of 50 flags there are bits set to one, then the control unit proceeds to the execution of block 5-3 of the algorithm and the process of reading segments continues until the register of flags 50 is reset, which will be fixed by changing the position of the line 29. In this case the signal control unit on line 26 performs the unloading of queue memory 49 (block 5 of the priority 5-13) and proceeds to execution of block 5-1 of the algorithm on phi | .one.

The operation algorithm of the control device when unloading data from the buffer memory is presented in FIG. After initial

0 of the installation, the control unit cyclically analyzes the state of the data readiness line 35 at the output of the fragment address block 8. When loading data into block 8, the fragment address values on bus 11 and

5 bits of the bus 22 with some delay are installed on the output tires 33 and 34 of the block 8, the output 35 is set to one. The control unit analyzes the state of the bus 34 (block of the algorithm 6-2), and if additional segments are needed to fetch a fragment from data memory 5, i.e. bus 34 contains a non-zero code value, the control unit stores its value (algorithm block 6-3). Next, the control unit cyclically analyzes the state of the data readiness line 41 at the output of block 6 (algorithm block 6-2). If the data has been loaded, the signal control device on line 36 connects the output

the bus of block 9 to the address inputs 43 of memory block 5 (algorithm block 5-6) and loads the required data segment into memory block 5 by a signal on line 38 (algorithm block 6-6). After that, the signal control unit on line 46 and the signal on line 39 unloads the memory block 9 of the input address queue and the memory block of the data queue (algorithm block 6-7), subtracts one from the internal counter of the number of segments (algorithm block 6- 8) and, if it is zero, repeats the blocks of the algorithm 6-4, 6-5, 6-6, 6-7, 6-8 until the internal counter is zeroed. When all the required signals are loaded, the signal control unit on line 36 switches switch 4 to a position that allows 43 bits of bus 33 to go to the output (algorithm block 6-10), starts the reading cycle of signal block 5 on line 37 (algorithm block 6-11) and after the time required for reading the data, sets the data readiness signal in block 14 (algorithm block 6-12). Then, after the delay required for data transmission to an external receiving device (algorithm block 6-13), the control unit unloads the block 8 (algorithm block 6-14) by a signal on line 38 and proceeds to block 6-1 algorithm ma figure 6.

The proposed conveyor buffer memory device is intended for in-line processing of two-dimensional 4x4 element size data fragments. Data with an arbitrary address is retrieved from the source data memory into the buffer memory device and is written to the output data memory by the output processor. The memory of the initial data with the capacity of the MxM elements, as well as the memory of the block of data storage devices with the capacity of the elements (M, N, L, P - powers of 2) are divided into 4x4 element segments. The memory of the source data contains M / 4xN / 4, and the buffer memory contains L / 4xP / 4 segments. A segment is a data unit when data is loaded into a buffer memory. Address memory block 1 contains L / 4 P / 4 memory cells (one for each segment) in which the higher bits of the segment addresses are stored. When generating a fragment address with an arbitrary address, its elements may lie in different segments. In block 1, the data contained in the data memory block in four neighboring segments are monitored in parallel. In the absence of data, the required segment is loaded from the original memory.

data, after which it is possible to sample at an arbitrary address. Depending on the address loading from one to four segments is possible. In order to organize parallel control of data, as well as parallel sampling of a fragment at an arbitrary address, blocks 1 and 5 have been used to add address calculation nodes and cyclic data shift nodes, which ensures parallel sampling.

In block 1 of the data memory (DB) with the help of sixteen pairs of adders and block 83 of the cyclic shift of data at the output of sixteen memory modules, an arbitrary sample of a 4x4 fragment of the form is implemented

, n-1, n am-1, n + 1i Egp-1.n + 2A (m, n) 3m.n-1 3m, n Itn.n-3m, n + 2 (1)

3m + 1, n-1 Etn.n 3m + 1, n + 1 3m + 1.n + 2 3m + 2, n-1 3m-t-2.n .n + 1 3m + 2.n + 2

where t, n are the indices defining the fragment address, with 0 m L and O n p; at.n - the central element of the fragment.

With a linear organization of memory, when the memory data is arranged line by line, the addresses of the elements forming the square matrix (1) can be represented by the following:

A (m-H, n + j) P (m + l) + (n + j), (2)

where I and j are integers varying within -1 I 2, -1 j 2;

P is the length of the string;

type - coordinates of the central element.

In the proposed buffer memory device, the elements of the two-dimensional array are distributed over sixteen memory modules in accordance with the distribution function

a (m, n) 4 JS, + i

(3)

where is the symbol denoting the operation of taking the remainder of the division;

O. (m, n) - memory module number (0)

The addresses of the elements of the array in the memory modules are determined by the formula

A (m.n) -ЈjЈ + J. (4)

where is the symbol denoting the operation of taking the whole part of the division.

Thus, the position of the array element in the memory is determined by the memory module number and the address inside the module, calculated using formulas (3) and (4).

The use of function (3) leads to a violation of the natural arrangement of the elements of the fragment extracted from the memory. To restore the order of the data, block 83 is used (Fig. 10), which is a combinational circuit consisting of two stages. The first cascade performs a cyclic shift within the four data groups and controls the bits n0 and the full memory address, the second cascade cyclically shifts the data groups themselves and controls the bits t0 and mi the full memory address.

Let MxN be the dimension of the data array stored in the original image memory, LxP be the dimension of the data array stored in the buffer storage device DB. The bus width of the full memory address of the two-dimensional fragment (1) can be represented by

Ap (toga + 1002) + (iog2 +

+ Iog2 Ј) + 4. (5)

where Ar is the address bus width

The expression in the first parentheses represents the highest bits of the full memory address, and second, the address bits of the segment in the database containing the central element am.n of the matrix (1) Digit 4 represents the bits m0, mi, n0, n addressing the element inside the segment. The highest bits of the full memory address are stored in the BA, whose word length is equal to

D-log2 Y + ° 92 -jj + T,

where T is the additional binary bit of data truth.

The bit T is zeroed before the start of the buffer memory session and is set to one when the segment address is written to the BA. The use of bit T prevents the BA comparators from malfunctioning in the absence of true data in the database. The BA capacity is determined by the DB capacity, i.e. the number of segments contained in the database, therefore, the address of the BA bus contains loga -ts +

o + loga -t binary bits Due to the fact

that in the database a fragment is sampled with a transition across the segment boundaries, the address bus of the database (block 5) also includes bits m0, mi, n0, ni. The elements of fragment (1) can be in one, two or four segments. For the purpose of parallel testing for the presence of

d)

0

five

0

five

0

five

0

five

0

five

()

or the absence of the required segments in the database in BA two-dimensional sampling of a 2x2 element of the form is organized

Bm.n bi-i, j B (i, j)

bi j-1 bi, j where I, j are the indices defining the address

LP

fragment, with 0 i S d, 0 and -v-;

bi.j is the central element of the fragment. Array elements of dimension x

 distributed over four memory modules in accordance with the distribution function

a (i, j) 2 | + i

where a (I J) is the number of the memory module, and

0 and 3.

The addresses of the elements of the array in the memory modules are determined by the formula

A (l, J) -f Ј + Ј,

As in the data memory, the use of function (7) leads to the dependence of the order of the location of the output data of the memory modules A0, AI, Aa, Az on the address of the segments to be extracted. However, in contrast to the data permutation scheme used in the database, the order of the comparison flags is subject to adjustment.

During data loading by an external master device, data pumping from the source data memory is required only for a part of the fragment addresses. In block 8, the lower bits of all fragment addresses are loaded. Each loaded word is accompanied by a three-bit code containing information about the number of data segments to be loaded into the buffer memory. In block 49, the addresses of the base data segments and four flags are specified, determining the necessity of loading the four adjacent data segments. The base segment address and flags are formed in block 1. Each data word loaded into block 49 corresponds to a specific fragment address loaded into block 8. Prefetching is performed using the memory of the queue of blocks 6, 8, 9, 49 in the proposed buffer memory device data and parallel operation of data loading and unloading algorithms

Let the memory of the fragment address queue contain sixteen cells, the external driver generates sixteen full data fragment addresses on bus 11, and only data for the first fragment address and the sixteenth will be required to download data. After the sixteenth address is loaded into block 8, output 12 is set to O, prohibiting further loading. In block 49 will be loaded two words corresponding to the first and last addresses of the fragments. After loading in block 8 the first fragment address, and in block 49 of the address of the base segment, control device 7 loads the data (algorithm in FIG. 5) and simultaneously analyzes the state of line 41 (algorithm in FIG. 6). When the data necessary for sampling the first fragment is loaded and it will be read from memory block 5, the control unit executes in parallel two algorithms — sequential reading of data fragments from the second to the fifteenth, for which data pumping from block 5 is not needed and data loading in block 6 of the source data memory necessary for reading the sixteenth fragment. When the data of the sixteenth fragment is required, it will already be loaded into block 6.

In the proposed buffer memory, standard FIFO type memory blocks (FIRST INPUT; FIRSTOUTPUT) are used as memory block 9 of the input address queue and data queue memory block 6, similar to blocks 8 and 49 shown in Fig. 4 (a) and 4 (b).

/

Claims (2)

Claim 1. Conveyor buffer memory for image processing systems comprising a control unit, an address storage unit, a data storage unit, an address conversion unit, an address switch, wherein the first and second outputs of the control unit are connected to the read and write inputs of the memory unit data, the third and fourth outputs - with the first and second control inputs of the address translation unit, the seventh output - with the control input of the address switch, the fifth and sixth outputs of the control unit are ready outputs output data and addresses of the device segment, the first input of the control unit — the readiness input of the device input data; the output of the address switch is connected to the address input of the data storage unit; the address input and data input of the address memory block are connected to the corresponding inputs of the full address of the device fragment; The data memory is an information output of the device, the output of the address conversion block is the address output of the device, characterized in that, in order to improve the speed of the device, a block is entered into it the memory of the output address queue, the memory queue of the input address g, the data queue memory block, the data fragment address memory block, the first information input of the data fragment address memory block and the first control input of the output address queue memory block are connected to the corresponding inputs of the full address of the device fragment, the second output of the address translation block is connected to the information input of the memory block of the input address queue, the output of which is connected to the first information input of the switch ad rez, the first control output of the output address queue 0 is connected to the write enable input of the memory block of the address, the first and second information outputs of which are connected respectively to the first and second information inputs of the queue memory block 5 output addresses, the second and third control outputs of the memory block of the output address queue are connected to the third and fourth control inputs of the address conversion block, whose information input is connected to the first information output of the memory block of the output address queue the addresses of the data fragments, the memory of the address and the memory of the queue of the output address are combined and are the input gate for recording the input address of the device, the output of the memory block of the address of the memory is gmentov data is output prohibition recording device, the second 0 the information output of the memory block of the output address queue is connected to the second information input of the memory block of addresses of data fragments, the eighth and ninth outputs of the control block are connected to 5 second and third control inputs of the memory block of the output address queue, second and third inputs of the control block with the fourth and fifth control outputs of the memory block of the output address queue queue, 0, the fourth and fifth inputs of the control unit are connected to the output of data readiness and data overflow of the data queue memory block, respectively, the data unloading input and the data load input of the data queue memory 5 are connected to the tenth and eleventh outputs of the control unit, the information input of the memory block These data queues are the device information input, the output of the data queue memory block is connected to the information the data memory input, the twelfth and thirteenth outputs of the control unit are connected to the data load and unloading inputs of the memory queue of the input address, the fourteenth output of the control unit is connected to the data unloading input of the data fragment address memory block addresses of data fragments are connected respectively to the second information input of the switch and to the sixth input of the control unit, the seventh input of which is connected to the readiness output of the output data of the memory block addr cos data fragments 2. Pop-up device 1, characterized in that the output address queue memory block contains a masking and cyclic shift node of comparison flags, a flag register, an encoder and a decoder, a queue memory node, a unit counter, the first information input of the block connected to the first information input of the queue memory node, the first information output of which is the first information output of the block, the second information output of the queue memory node connected to the data input of the flag register, the output of the flag register connected to the input w ifrator whose first exit connected to the fifth control output of the block, the second and third outputs of the encoder are the second and third control outputs of the block, respectively, and are connected to the information input of the decoder pat gate whose input is the third control input of the block, the first control and the second information inputs of the block connected to the manager and the information inputs of the mask node and the cyclic shift of the comparison flags, the first output of which is connected to the second information input of the queue memory node and the input of the unit counter, the second output of the masking and cyclic shift of the comparison flags is the first controlling output of the block, the decoder outputs are connected to the flag register reset inputs, the ready output the queue memory node is connected to the flag register gating input and is the fourth control output of the block, the unloading memory of the queue memory node is the second control input of the block, the first output of the unit counter is connected to the write enable input of the memory node of the queue, the second output is the second information output of the block; the input entry gating of the queue memory node connected to the gating input of the recording entry device address. 15 1 18 Tgpf 69aSil FIG 4 (a) FIG. 4 (8) 1 G sh Phage. five Fig.b Fig.8 43 L 44 -I 41 81, 44 - 41 44 - W /five 57 18 41 L / 3 - W /five 84 73 - / FIG. 9 FIG. ten